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Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ
Resource (Slides) - Apr 04, 2024 by Avinash Agrawal - Siemens EDA
In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
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How and Why We Adopted Questa Core in the Development of Quantum Computers
Seminar - Apr 04, 2024 by Jan Marjanovic - Atom Computing
This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.
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How and Why We Adopted Questa Core in the Development of Quantum Computers
Resource (Slides) - Apr 04, 2024 by Jan Marjanovic - Atom Computing
This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.
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How We Use PCIe Verification IP Across Multiple Projects
Seminar - Apr 04, 2024 by Weiping Guo - Marvell
In this session we will discuss how Marvell delivers successful products and drives the market by with a structured design and verification methodology that reflects this philosophy. Specifically, we will dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP.
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How We Use PCIe Verification IP Across Multiple Projects
Resource (Slides) - Apr 04, 2024 by Weiping Guo - Marvell
In this presentation we will discuss how Marvell delivers successful products and drives the market by with a structured design and verification methodology that reflects this philosophy. Specifically, we will dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP.
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Customer Case Studies with AI/ML in Verification
Seminar - Apr 04, 2024 by Karim Ameziane - Siemens EDA
In this session we will share some results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: in order to apply advanced ML techniques to bring more value to verification, we show how to focus on building data assets that will put a verification team on the path to ML success.
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Customer Case Studies with AI/ML in Verification
Resource (Slides) - Apr 04, 2024 by Karim Ameziane - Siemens EDA
In this session we will share some results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: in order to apply advanced ML techniques to bring more value to verification, we show how to focus on building data assets that will put a verification team on the path to ML success.
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The Importance of Simulation in the Pursuit of Absolute Speed!
Resource (Verification Horizons Blog) - Apr 02, 2024 by Sunil Sahoo
I recently had an opportunity to talk to someone who worked in the high-frequency trading (HFT) sector a few years ago. I wanted to know how they performed their functional simulations. If you know anything about HFT or low-latency trading, you know that those engineers are very secretive and don’t divulge a lot of details about what their FPGA design-verification process entails.
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Questa Check Connect Fact Sheet
Resource (Fact Sheet) - Apr 01, 2024 by Nicolae Tusinschi
Questa Check Connect offers a distinct approach for verifying interconnect integrity within designs. It facilitates scalable verification for extra-large System-on-Chips (SoCs) through automated and exhaustive formal analysis. The solution is designed for easy deployment, delivering unique capabilities for conclusive results in complex connectivity challenges that surpass traditional capacity limits.
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Questa Check Register Fact Sheet
Resource (Fact Sheet) - Apr 01, 2024 by Nicolae Tusinschi
Questa Check Register guarantees the alignment of register implementations with specifications. It seamlessly reads RTL descriptions and register specifications from either IP-XACT or a custom format, then generates assertions for verifying memory-mapped registers. It promptly detects all RTL related functional concerns tied to registers. Additionally, it offers effortless monitoring of progress through the Questa verification management tool.
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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Resource (Slides) - Mar 27, 2024 by Rick Koster
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity.
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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Webinar - Mar 27, 2024 by Rick Koster
This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.
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In Memoriam: Chris Spear
Resource (Verification Horizons Blog) - Mar 14, 2024 by Tom Fitzpatrick
Our friend and colleague Chris Spear passed away suddenly. He was a long-time veteran of our industry and was known and respected by many.
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Resource (Slides) - Mar 14, 2024 by Atul Sharma
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Webinar - Mar 14, 2024 by Atul Sharma
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.
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Get your free copy of the IEEE 1800-2023 SystemVerilog LRM
Resource (Verification Horizons Blog) - Mar 04, 2024 by Dave Rich
At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog standard. After a year of two rounds of balloting, the final revision is being published. The great news is many of these “new” features are already available in existing tools, or being worked on.
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Verification Horizons
Article - Mar 01, 2024 by Tom Fitzpatrick
The advent of new technologies - such as constrained-random data generation, assertion-based verification, coverage-driven verification, and formal model checking to name a few - have changed the way we see functional verification productivity. An advanced verification process enables users to manage the application of these new technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs have been covered.
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Enhancing PCIe Verification: How to Step Off the Map
Article - Mar 01, 2024 by Irivinti Shiva Teja - Siemens EDA
This article intends to propose a range of strategies that an RC might use to ‘generate’ addresses that fall outside the standard scope, along with a detailed examination of the subtle complexities involved. Initially, we will explore two relatively simple methods to accomplish this. Following that, we will analyze the limitations inherent in these methods.
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Tool Assisted Debug in Visualizer
Article - Mar 01, 2024 by Richa Jha - Siemens EDA
Verification is one of the primary challenges in current times when designs are huge, and corresponding testbenches are equally large. Both the design and testbench work together to fulfill the desired expectations of the designer. Everything goes well until the simulation does not work as expected. This is where Visualizer, the debug platform, plays a crucial role in figuring out where the problem lies. Visualizer requires multiple databases to provide the debug features.
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Formal Verification: An Introduction and Exploration of Challenges
Article - Mar 01, 2024 by Yusuf Eren - ANKASYS
Nowadays, the formal verification is getting more popular compared to the conventional simulation-based verification. The main idea behind the formal verification is to mathematically prove or disprove the correctness of a design with respect to the specification or requirement and ensure that the design behaves as intended under all possible scenarios. To achieve this, the formal verification tools are using Satisfiability Modulo Theories (SMT) solver engines.
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Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App
Article - Mar 01, 2024 by Chuck Banken, Chenguang Li - Siemens EDA
Hardware-Assisted verification (HAV) with emulation is widely regarded as crucial for successfully designing, verifying, and deploying large ASICs and even FPGAs. An emulator is a major capital investment, and customers are highly motivated to get the maximum benefit from their expenditure.
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A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Resource (Recording) - Mar 01, 2024 by Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces
This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.
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A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Article - Mar 01, 2024 by Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces
This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.
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DVCon 2024 – Verify Real Number Models
Resource (Verification Horizons Blog) - Feb 26, 2024 by Mariam Maurice - Siemens EDA
Do you like to solve puzzles? I do, and I think every engineer does. Since we are solving puzzles every day, there is always a masterpiece that could complete your puzzle. The masterpiece could be any internal piece of puzzle that could complete your final image. Verifying the complete image of your puzzle by putting internal pieces one after another, could help make you reach the final picture.
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UVM Objections at DVCON US 2024 – and Grape Jelly
Resource (Verification Horizons Blog) - Feb 22, 2024 by Rich Edelman
It’s been a while – busy. Too busy to be in the garden. But last fall we realized the grape plants in the yard produced a ton of grapes – at least it looked like a ton to us. What to do? Instead of letting the birds eat all the grapes, we decided to make jelly. I’ve made jelly before – it’s not hard, but it can (and did) go wrong. (See – already like the UVM)