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2076 Results

  • DO-254 in Simple Terms

    In this session, you will be introduced to DO-254 from a designer’s perspective in layman’s terms and will be gain a fundamental understanding of what DO-254 is and its applications.

  • DO-254 in Simple Terms

    In this session, you will be introduced to DO-254 from a designer’s perspective in layman’s terms and will be gain a fundamental understanding of what DO-254 is and its applications.

  • Introduction to DO-254

    The purpose of this track is to provide engineers or technical leads with basic understanding of DO-254 key concepts. DO-254 has been around for over 15 years and has been applied almost exclusively in the commercial Aerospace industry. Because it has been focused on a subset of the electronic hardware market, many engineers and companies have little to no knowledge of DO-254.

  • UVM 1800.2 and the New & Improved Cookbook

  • A Fresh Look at Creating a UVM Environment - UVM Framework

  • A Fresh Look at Creating a UVM Environment - All Slides

  • A Fresh Look at Creating a UVM Environment - Introduction

  • Vista Virtual Prototyping

  • Visualizer Debug Introduction

  • UVM 1800.2 & The New and Improved UVM Cookbook

  • UVM 1800.2 & The New and Improved UVM Cookbook

    This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.

  • UVM

    The (2018) version conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond. Find all the UVM methodology advice you need in this comprehensive and vast collection.

  • UVM-2017 v0.9 Library Code for IEEE 1800.2

  • UVM 2017-1.0 Reference Implementation

  • UPF Information Model: The Future of Low-Power Verification Today

    The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

  • UPF Information Model - The Future of Low-Power Verification Today

    The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

  • Power Aware Simplifies Parametric PA-SIM Regression

  • Portable Stimulus versus UVM: What's the Difference?

    We compare the Accellera Portable Test and Stimulus Standard (PSS) with the Universal Verification Methodology (UVM), and ask exactly what the difference is between the two when it comes to generating stimulus for hardware verification and SoC verification.

  • Data Mining for SoC Level Performance

    This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

  • Validating Your SoC is True to Requirements

  • DAC 2018 Academy PDF Presentation: UVM 1800.2 & The New and Improved UVM Cookbook

  • Portable Stimulus: A New Hope

    This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology.

  • Building An Integrated Verification Flow

    While a lot of information is produced to introduce and support individual verification techniques, methods for applying a variety of verification techniques in a complementary way are harder to come by. In this session, we’ll discuss the factors and decisions that go into building an effective verification flow including what techniques to use and how they can be used together.