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Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps

Paper - Jul 07, 2019 by Madhur Bhargava - Siemens EDA

The effective verification of low power designs has been a challenge for many years now. The IEEE 1801 standard for modeling low power objects and concepts is continuously evolving to address the low power challenges of today’s complex designs. One of the traditional yet effective way to verify the design is to write SystemVerilog (SV) assertions to ensure that right design behavior is met.
Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps

Resource (Paper (.PDF)) - Jul 07, 2019 by Madhur Bhargava - Siemens EDA

The low power designs today are incredibly complex with intricate power architecture. A thorough low-power verification is must for such designs as any power bug left can cause huge setback. In this paper we discuss the challenges with the current low-power design checking and how a proposed method can be addressed with the help of UPF 3.0.
Transaction Recording & Debug with Questa & Visualizer

Webinar - Jun 20, 2019 by Rich Edelman

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.
Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Webinar - Jun 20, 2019 by Ashish Amonkar

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Resource (Paper (.PDF)) - Jun 11, 2019 by Kurt Takara

Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs. This methodology is a 3-step process that provides a requirements-based approach for RDC design and verification.
A Specification-Driven Methodology for the Design and Verification of RDC Logic

Paper - Jun 11, 2019 by Kurt Takara

With the increasing complexity of today's System-on-a-Chip (SoC) designs, reset architectures have also increased in complexity. Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset-domain crossing (RDC) paths in large SoC designs.
Reusable UPF - Transitioning from RTL to Gate Level Verification

Resource (Paper (.PDF)) - Jun 11, 2019 by
What's Missing and What Should Be Next for SystemVerilog

Resource (Slides (.PDF)) - Jun 03, 2019 by Cliff Cummings

Cliff Cummings shares possible new features that would help engineers create more concise designs while making fewer mistakes. The proposed features would also increase customer satisfaction with EDA tools and require fewer queries and complaints to EDA vendors.
Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer

Resource (Slides (.PDF)) - Jun 03, 2019 by Sumit Vishwakarma

In this session we will dive into a simple scenario and demonstrate how you can take advantage of Symphony and the Visualizer Debug Environment to debug RNM boundary scenarios in case of a functional failure.
Debugging Your Design in a Heterogeneous Environment

Resource (Slides (.PDF)) - Jun 03, 2019 by Rich Edelman

In this session we will address debug needs of today's complex environment using Questa Visualizer Debug.
Debugging Your Design in a Heterogeneous Environment

Conference - Jun 03, 2019 by Rich Edelman

Designs are dramatically more complex today, often consisting of huge subsystems and IP (both legacy and acquired). The verification process of these complex designs involves Simulation, emulation, static, formal, UVM, power aware, etc... Users debugging these complex heterogeneous environments are looking for a unified debug solution that will present data in context and make engines/technologies transparent.
SystemC FMU for Verification of Advanced Driver Assistance Systems

Article - Jun 03, 2019 by Keroles Khalil, Magdy A. El-Moursy - Siemens EDA

An integrated framework to simulate electronic systems (including digital and analog devices) with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting of many electronic control units (ECUs), is modeled to simulate the mechatronic system functionality. The recently developed functional mock-up interface standard approach is used to create a model for a complex cyber-physical automotive system.
Fun with UVM Sequences - Coding and Debugging

Article - Jun 03, 2019 by Rich Edelman

In a SystemVerilog UVM 2 testbench, most activity is generated from writing sequences. This article will outline how to build and write basic sequences, and then extend into more advanced usage. The reader will learn about sequences that generate sequence items; sequences that cause other sequences to occur and sequences that manage sequences on other sequencers. Sequences to generate out of order transactions will be investigated. Self-checking sequences will be written.
Creating Tests the PSS Way in SystemVerilog

Article - Jun 03, 2019 by Matthew Ballance

Portable Stimulus is one of the latest hot topics in the verification space. Siemens EDA, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test and Stimulus Standard, a standard language that can be used to capture Portable Stimulus semantics.
Formal Bug Hunting with “River Fishing” Techniques

Article - Jun 03, 2019 by Mark Eslinger

Formal verification has been used successfully to verify today’s SoC designs. Traditional formal verification, which starts from time 0, is good for early design verification, but it is inefficient for hunting complex functional bugs. Based on our experience, complex bugs happen when there are multiple interactions of events happening under uncommon scenarios.
Auto-Generating Implementation-Level Sequences for PSS

Article - Jun 03, 2019 by Amanjyot Kaur, Louie De Luna - Agnisys

The Portable Test and Stimulus Standard (PSS) v1.0a aims to help the user describe the high-level test intent and create code for any downstream verification platform.
UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs

Article - Jun 03, 2019 by George Stevens - DesignLinx Solutions

The basis of this article was derived from practical experience. The scenario was this: “Here is a DUT specification, we have no UVM environment for you to start with as a template, so go and find out how to generate one with Siem ens EDA ’s UVM Framework (UVMF) template generation methodology.”
SystemVerilog Constrained Random Handbook

Resource (Reference Documentation) - May 28, 2019 by
Random Directed Low-Power Coverage Methodology - A Smart Approach to Power Aware Verification Closure

Resource (Paper (.PDF)) - May 22, 2019 by Madhur Bhargava

With the advancement in the technology, low-power design and its verification is becoming more complex. Today’s chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels.
Debugging Functional Coverage Models: Get the Most of Out of Your Cover Crosses

Resource (Paper (.PDF)) - May 13, 2019 by Mennatallah Amer

Applying hole analysis on each cover cross independently can lead to misleading results and is sometimes prohibitive due to the sheer number of crosses. Additionally, we introduce a metric, hole effect, that is proportional to the coverage gains that would result upon resolving the highlighted hole. We evaluate our approach on a real processor’s data processing unit to validate its applicability and usefulness for debugging complex functional coverage models.
Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses

Paper - May 13, 2019 by Mennatallah Amer - Siemens EDA

Functional coverage models have grown in complexity to account for the increasing demands of designs today. Traditional and even advanced analysis techniques have yet to evolve to provide the verification engineer with actionable insights on how to debug their functional coverage model. In this paper, we generalize advanced hole analysis techniques to be able to get the most out of cover groups containing multiple cover crosses.
Block level testbench (.tgz)

Resource (Tarball) - Apr 19, 2019 by
Verification Acceleration for ASIC and FPGA Designs

Resource (Slides (.PDF)) - Apr 09, 2019 by Jerry Grula - Siemens EDA

Modeling large integrated circuits for the workloads required for verification takes more computing than can be accomplished on CPU farms with 1000s of CPUs for many years.
Don’t Do It Yourself: Questa VIP Accelerates UVM Testbench Development

Resource (Slides (.PDF)) - Apr 09, 2019 by Tom Fitzpatrick

This session will discuss writing constraints to characterize stimulus and configuration, creating prediction models, and defining coverage models with rapid testbench development utilizing the Questa Verification IP configurator to create high quality verification environments.
No Testbench? No Problem! We Have a (Formal) App for That

Resource (Slides (.PDF)) - Apr 09, 2019 by Chris Rockwood - Siemens EDA

Formal verification uses mathematical and algorithmic methods to prove exhaustive results, requiring no testbench or stimulus.