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Portable Stimulus: Is It Revolution or Evolution?

Conference - Jul 15, 2019 by Tom Fitzpatrick

Many claim the new Portable Test and Stimulus Standard. (PSS) from Accellera will ignite the next revolution in SoC and Electronic System functional verification. Revolutionary innovation seeks to adapt the world to new and better ideas; yet it can be disruptive, expensive and produce unpredicted outcomes.
Portable Stimulus: Is It Revolution or Evolution?

Resource (Slides (.PDF)) - Jul 15, 2019 by Tom Fitzpatrick

In this session, you will learn how Reuse can be the Evolution that enables the PSS Revolution.
An Emulation Strategy for AI and ML Designs

Conference - Jul 15, 2019 by Vijay Chobisa

The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session.
An Emulation Strategy for AI and ML Designs

Resource (Slides (.PDF)) - Jul 15, 2019 by Vijay Chobisa

The emergence of Artificial Intelligence is the “next big thing” in the overall The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges.
Tessent: DFT Enablement for AI Devices

Conference - Jul 15, 2019 by Geir Eide

Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
Tessent: DFT Enablement for AI Devices

Resource (Slides (.PDF)) - Jul 15, 2019 by Geir Eide

In this session, we'll learn about some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed
Deep Learning Accelerator Using HLS

Resource (Slides (.PDF)) - Jul 15, 2019 by
Streamlining Plan & Requirements Driven Verification

Resource - Jul 12, 2019 by
Improving Verification Throughput of Today’s Complex Mixed-Signal ICs

Resource (Slides (.PDF)) - Jul 12, 2019 by
Selecting the Most Productive SoC Design Verification Techniques

Resource (Slides (.PDF)) - Jul 12, 2019 by
Veloce HYCON - OS-aware IP Development Solution

Resource (Slides (.PDF)) - Jul 12, 2019 by
RISC-V Core and SoC: Compliance, Verification, Customization

Resource (Slides (.PDF)) - Jul 11, 2019 by Larry Lapides
Emulation to Prototype - What’s Eating Your Productivity?

Resource (Slides (.PDF)) - Jul 11, 2019 by
Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity

Resource (Slides (.PDF)) - Jul 11, 2019 by Tom Fitzpatrick

In this session, you will learn how you to use Portable Stimulus to leverage the built-in infrastructure in QVIP and your UVM environment to realize truly coverage-driven scenario-level functional coverage to keep you ahead of the productivity curve.
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification

Webinar - Jul 10, 2019 by Kurt Takara

This session explains the importance of a complete Clock-Domain Crossing (CDC) methodology to produce error-free silicon.
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification

Resource (Slides (.PDF)) - Jul 10, 2019 by Kurt Takara

This session explains the importance of a complete CDC methodology to produce error-free silicon.
Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps

Paper - Jul 07, 2019 by Madhur Bhargava - Siemens EDA

The effective verification of low power designs has been a challenge for many years now. The IEEE 1801 standard for modeling low power objects and concepts is continuously evolving to address the low power challenges of today’s complex designs. One of the traditional yet effective way to verify the design is to write SystemVerilog (SV) assertions to ensure that right design behavior is met.
Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps

Resource (Paper (.PDF)) - Jul 07, 2019 by Madhur Bhargava - Siemens EDA

The low power designs today are incredibly complex with intricate power architecture. A thorough low-power verification is must for such designs as any power bug left can cause huge setback. In this paper we discuss the challenges with the current low-power design checking and how a proposed method can be addressed with the help of UPF 3.0.
Transaction Recording & Debug with Questa & Visualizer

Webinar - Jun 20, 2019 by Rich Edelman

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.
Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Webinar - Jun 20, 2019 by Ashish Amonkar

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Resource (Paper (.PDF)) - Jun 11, 2019 by Kurt Takara

Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs. This methodology is a 3-step process that provides a requirements-based approach for RDC design and verification.
A Specification-Driven Methodology for the Design and Verification of RDC Logic

Paper - Jun 11, 2019 by Kurt Takara

With the increasing complexity of today's System-on-a-Chip (SoC) designs, reset architectures have also increased in complexity. Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset-domain crossing (RDC) paths in large SoC designs.
Reusable UPF - Transitioning from RTL to Gate Level Verification

Resource (Paper (.PDF)) - Jun 11, 2019 by
What's Missing and What Should Be Next for SystemVerilog

Resource (Slides (.PDF)) - Jun 03, 2019 by Cliff Cummings

Cliff Cummings shares possible new features that would help engineers create more concise designs while making fewer mistakes. The proposed features would also increase customer satisfaction with EDA tools and require fewer queries and complaints to EDA vendors.
Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer

Resource (Slides (.PDF)) - Jun 03, 2019 by Sumit Vishwakarma

In this session we will dive into a simple scenario and demonstrate how you can take advantage of Symphony and the Visualizer Debug Environment to debug RNM boundary scenarios in case of a functional failure.