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DVCon (124)
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Aerospace (115)
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RTL (104)
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CDC (88)
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ISO 26262 (69)
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Components (67)
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DUT-TB (64)
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Registers (54)
Code Example (52)
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Generative AI (51)
Tests (51)
Industry Trends (49)
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Wilson Research Group (49)
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SoC (44)
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VHDL (43)
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Avery Verification IP (40)
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Trends (39)
Compliance (38)
Emerging Trends (38)
OOP (38)
RISC-V (38)
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Equivalence Checking (36)
Formal Analysis (36)
PSS (36)
DAC (35)
IEEE 1801 (35)
Power Management (35)
TLM 2.0 (35)
Configuration (34)
Connectivity (34)
IC/ASIC (34)
Questa One (34)
AMS (33)
Artificial Intelligence (33)
Factory (33)
Objects (33)
Power Domain (33)
WRG (33)
Code Coverage (32)
Scoreboard (32)
ASIC (31)
DO-254 (31)
Reset-Domain Crossing (31)
Verification Efficiency (31)
Bug Hunting (30)
Metastability (30)
Modeling (30)
TLM (30)
osmosis 2022 (30)
Accellera (29)
CDC Methodology (29)
PCIe (29)
Properties (29)
Register Model (29)
Reset Issues (29)
Safety Analysis (29)
Classes (28)
Safety Architecture (28)
Test Planning (28)
UVM Debug (28)
Introduction to UVM (27)
Lint (27)
Patterns (27)
Requirements Traceability (27)
Synchronization (27)
Verilog (27)
Coverage Analysis (26)
Coverage Metrics (26)
Design Optimization (26)
Functional Simulation (26)
Property Checks (26)
Waveform (26)
Abstraction (25)
Analytics (25)
Archive (25)
Block Level (25)
Asynchronous Clock (24)
Cookbook (24)
Design Trends (24)
Driver (24)
Fault Campaign (24)
Lifecycle (24)
Netlist (24)
Object Oriented Programming (24)
Requirements (24)
Testplan (24)
UVM Basics (24)
Co-Emulation (23)
FSM (23)
osmosis 2024 (23)
Assurance (22)
Data-driven Verification (22)
Non-Trivial Bug Escapes (22)
Performance (22)
Proofs (22)
System Level (22)
VRM (22)
Arrays (21)
Big Data (21)
Collaborative Analysis (21)
Config_db (21)
Constrained Random Verification (21)
Covergroup (21)
Interactive Mode (21)
Interoperability (21)
Memory (21)
PCI Express (21)
Packages (21)
U2U (21)
osmosis 2023 (21)
Acceleration (20)
Advanced UVM (20)
C (20)
Chiplets (20)
Constrained Random Stimulus (20)
Data Types (20)
Design Constructs (20)
Functional Verification Study (20)
Hardware Fault (20)
Python (20)
Signal (20)
X-Tracing (20)
Continuous Integration (19)
DFT (19)
Power States (19)
Requirements Management (19)
Safety Mechanism (19)
Safety Workflow (19)
Scenario Generation (19)
Verification Closure (19)
Verification Practice (19)
Verification Run Manager (19)
Virtual Interface (19)
API (18)
Advanced Debug Techniques (18)
Automation (18)
Code Generator (18)
Configuration Database (18)
Controllers (18)
Coverage Points (18)
Polymorphism (18)
Sequence Item (18)
Sequencer (18)
State Space (18)
CDC Analysis (17)
Design Complexity (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Sequence Driver (17)
Testbench Automation (17)
U2U Europe (17)
UCIe (17)
Virtual Sequences (17)
BFMs (16)
Gate-Level (16)
HLS (16)
Reset-Domain Checking (16)
SLEC (16)
Universal Chiplet Interconnect Express (16)
Class Objects (15)
Continuous Integration System (15)
Data Models (15)
Expressions (15)
Inconclusives (15)
Intelligent Automation (15)
Power Intent (15)
QVIP Configurator (15)
Sub-system (15)
Variable (15)
osmosis Europe 2025 (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Customization (14)
DFT Verification (14)
FPGA Prototyping (14)
Failure Analysis (14)
Fault Simulation (14)
Glitches (14)
IC Reliability (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
NVMe (14)
Productivity Gap (14)
Register Layer Adapter (14)
Stimulus Generation (14)
UVMC Kit (14)
AXI (13)
Checkers (13)
Declaration (13)
Formal Application (13)
Functional Correctness (13)
Gate-Level Simulation (13)
Hardware Acceleration (13)
Interconnect (13)
Multi-Die (13)
Operators (13)
Python for Verification Series (13)
RDC Analysis (13)
Verification IQ (13)
X-Propagation (13)
ASIL (12)
Adoption Trends (12)
Agent (12)
Co-Simulation (12)
Coverage Models (12)
DVCon Japan (12)
Data Mining (12)
Environment Pattern (12)
Hierarchical Components (12)
Interrupts (12)
Iterations (12)
Parameterized Classes (12)
Randomization (12)
September 2021 - Volume 17 Issue 2 (12)
Strategy (12)
Tool Assessment (12)
Traceability (12)
Unit Testing (12)
Validation (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Configuration Object (11)
Connections (11)
Convergence (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DPI-C (11)
Fault Grading (11)
Generation (11)
High Speed (11)
Interview (11)
Isolation (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
PYUVM (11)
Predictive Analysis (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Test Environment (11)
VIQ (11)
Verification Process Overview (11)
AMBA (10)
Backdoor Accesses (10)
Breakpoint (10)
Class Handles (10)
Class Reference (10)
Command API (10)
Deadlock (10)
FPU (10)
Fault Analysis (10)
High-Level Synthesis (10)
Implementation Model (10)
Inheritance (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Metrics-Driven (10)
Model Checking (10)
Parallel Simulation (10)
Proof Coverage (10)
Property Debug (10)
RDC Methodology (10)
Report (10)
Reset Architecture (10)
Root of Trust (10)
SVA (10)
Safety Metrics (10)
Timing (10)
Unified Power Format (10)
Verification Architecture (10)
Verification Component (10)
osmosis 2025 (10)
1800.2 (9)
3DIC (9)
AI Algorithms (9)
Bitstream (9)
CDC Path (9)
CDC Protocol (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
Data Management (9)
Data Types and Procedural Statements (9)
Encapsulation (9)
Formal Assertion-Based Verification (9)
HPC (9)
Hardware Security (9)
Hierarchical Sequences (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Metastable (9)
Multi-Core Architectures (9)
PSL (9)
Parameter (9)
Power Analysis (9)
Power Logic (9)
Power Optimization (9)
RDC Violations (9)
Reconvergence (9)
Reference Model (9)
Retention (9)
SPI (9)
Scalable Verification (9)
Schematic (9)
Secure Data Path (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Testbench Architecture (9)
Testing Strategies (9)
Training (9)
UALink (9)
UCDB (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Waivers (9)
Whats New in Functional Verification (9)
Algorithms (8)
B/C/R Script (8)
Clock Gating (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
Floating-Point Units (8)
HDL Domain (8)
HTML Docs (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Mixed-Signal Design (8)
OSCI (8)
OVM2UVM (8)
Occurrence Property Pattern (8)
Overrides (8)
Phasing (8)
Pipelined (8)
Postsim (8)
Procedural Statements (8)
Release (8)
Reporting (8)
Reset Tree (8)
Safety (8)
Simulation Coverage (8)
State Machine (8)
State Transitions (8)
Sub-system Level (8)
Supply Set (8)
System Scaling (8)
UCIe 2.0 (8)
UVM Verification (8)
Voltage Domain Crossing (8)
osmosis 2023 A&D (8)
ADAS (7)
Agentic AI (7)
Bind (7)
Bounded Proof (7)
Cache Coherency (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
Data Transfer (7)
Design Assurance (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
Fork-Join (7)
Guidelines (7)
IP Blocks (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
Layering (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Modules (7)
Monitor (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Objections (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Power Estimation (7)
Predictors (7)
Property Analysis (7)
Safety Verification (7)
Schematic Debug (7)
Sequential Analysis (7)
Siemens EDA (7)
Specification (7)
Static Checks (7)
Structural Analysis (7)
Supply Network (7)
TLM FIFOS (7)
Technology Scaling (7)
Test Generation (7)
Test Verification (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
Transaction Recording (7)
VA Live 2023 - Huntsville (7)
Verification Complete (7)
X-Checking (7)
X-Corruption (7)
XML (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Bug Detection (6)
Computational Storage (6)
Corner-case Bugs (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
DDR (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Constraints (6)
Design Mitigation (6)
Design Patterns (6)
Digital Design (6)
Distributed Resource Management (6)
Electronic Hardware (6)
Fabric (6)
Flip-Flop (6)
Front and Back Door (6)
HDL (6)
HDM (6)
Hardware Designs (6)
Hierarchical Flow (6)
IP Integration (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PCIe Gen 7 (6)
Power Efficiency (6)
Pre-Silicon (6)
Random Faults (6)
Respins (6)
Slave (6)
Static & Formal Adoption (6)
Transaction-Level (6)
UCIe 3.0 (6)
UVM Forum (6)
UVVM (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
VHDL Testbench (6)
Verbosity (6)
Verification Effectiveness (6)
Visualization (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bus Functional Models (5)
Bus Protocol (5)
CHERI (5)
Callbacks (5)
Class Library (5)
Class Types (5)
Clock Propagation (5)
Co-Verification (5)
Concurrent Processes (5)
Constraint Solver (5)
Converters (5)
Coverage Holes (5)
DAC 2024 (5)
DSP (5)
Data Encryption (5)
Debug Methodology (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Digital Twin (5)
Dual Domains (5)
Error (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Formal Testbench (5)
HBM4 (5)
Hierarchical Data Model (5)
High-Speed (5)
IDE (5)
Implicit/Explicit (5)
In-Circuit Emulation (5)
JEDEC (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
March 2018 - Volume 14 Issue 1 (5)
Memory Usage (5)
NVM Express (5)
Namespaces (5)
Post-silicon Debug (5)
Precedence (5)
Processor Core Verification (5)
Prototyping (5)
Quirky (5)
Repository (5)
SSD (5)
SVUnit (5)
Sequence Library (5)
Simulink (5)
Spice (5)
Split Transactor (5)
State-Based Model (5)
Static Analyses (5)
Static RDC (5)
Stimulus Pattern (5)
Test Class (5)
Threads (5)
Transaction-Based Acceleration (5)
VA Live 2019 - Westford (5)
VA Live 2023 - Westford (5)
VA Live 2024 - Huntsville (5)
VA Live 2024 - Westford (5)
VA Live 2025 - Silicon Valley (5)
Verbose (5)
Virtual Methods (5)
Wishbone (5)
5G (4)
AI Model (4)
Bandwidth (4)
Batch and Debug (4)
Bi-Directional (4)
Bins (4)
Bit Width (4)
Black Boxing (4)
Bounded Model Checking (4)
C++ (4)
CXL (4)
Checkpoint (4)
Coverage Achievement (4)
DVFS (4)
Data Link (4)
Deprecated (4)
Design Analysis (4)
Design Hierarchy (4)
Determinism (4)
DisplayPort (4)
Driver Tracing (4)
Dynamic Power (4)
ECO (4)
ED-80 (4)
Enumeration (4)
Fault List (4)
Formal Closure (4)
Formal Methods (4)
HBM (4)
HDMI (4)
Hardware-Assisted Verification (4)
ICE Mode (4)
IEEE (4)
Implementation Driven Formal (4)
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In-Circuit Simulation (4)
In-System Test (4)
Initial States (4)
Instance (4)
LFM (4)
Large Language Models (4)
Low Latency (4)
Mathworks (4)
Metastability Injection (4)
Mitigation Architecture (4)
Non-Pipelined (4)
Non-Reset (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
Partitioning (4)
Phase Objections (4)
Phases (4)
Plusargs (4)
Protocol Checkers (4)
QoR (4)
Questa Design Solutions (4)
Race Conditions (4)
Register-Level Scoreboards (4)
Reset Handling (4)
Reset Signal (4)
Risk Mitigation (4)
Root Cause (4)
SVTB (4)
Specification Pattern (4)
Subscriber (4)
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Synergistic Verification (4)
Syntax (4)
Tcl/Tk (4)
Tessent Test Solutions (4)
Test Ranking (4)
Time Cone (4)
UART (4)
UEC (4)
UPF 4.0 (4)
USB (4)
Unified Coverage Database (4)
Unreachability (4)
Use Models (4)
Utilization (4)
VA Live 2023 - Austin (4)
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VA Live 2024 - Fremont (4)
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Vectors (4)
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X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
Affect Probability (3)
Airborne Electronic Hardware (3)
Analysis Components (3)
Analysis Port (3)
Application Lifecycle Management (3)
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Autonomous Systems (3)
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Boolean (3)
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CDC Signals (3)
CSI-2 (3)
Case Statements (3)
Cause-Effect (3)
Certification (3)
Class Variables (3)
Classifications (3)
Clocking (3)
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Coroutines (3)
Cover Method (3)
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Cryptography (3)
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Delay Loops (3)
Design Cycle (3)
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Development Environment (3)
Domain Specific Architectures (3)
Dual Top (3)
ESL (3)
Emulatability (3)
Exhaustive (3)
FWHW (3)
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Fibre Channel (3)
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Golden Model (3)
HLV (3)
Handles (3)
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Horizontal Reuse (3)
IC Design (3)
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JUnit (3)
July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
LRM (3)
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NRRs (3)
NoC (3)
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Observer (3)
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PCI-SIG (3)
PHY (3)
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Register Assistant (3)
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Routines (3)
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Semiconductor (3)
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Static Lists (3)
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Stream (3)
TBX (3)
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Test Coverage (3)
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Transfer Protocols (3)
Transitive (3)
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Type Casting (3)
UVM 1.1d (3)
UVM 1.2 (3)
UVM Rapid Adoption (3)
UVMC 2.3.0 (3)
UVMC 2.3.1 (3)
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Unidirectional (3)
Unreachable Code (3)
VHDL-2019 (3)
VIP - 3.1 (3)
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X-State (3)
2D/3D (2)
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IEEE 754 (2)
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Instantiate (2)
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Makefile (2)
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Memory BIST (2)
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Metric Analyzers (2)
Multi-Clock Designs (2)
Multi-Language Environment (2)
Network ID Mapping (2)
Noise Reduction (2)
On-Chip (2)
OnChip (2)
Open Bus Interface (2)
PAM4 (2)
Packet Transfer (2)
Parameter-to-Signal (2)
Partitioned Compile (2)
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