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FPGA Verification Maturity: A Quantitative Analysis

Resource (Slides (.PDF)) - Mar 26, 2020 by
Verify Thy Verifyer

Article - Mar 01, 2020 by Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks

Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases. The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.
Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs

Article - Mar 01, 2020 by Tomáš Vaňák - Codasip

Questa SLEC, the formal analysis app from Siemens EDA, was designed to automatically compare a block of code ("specification" RTL) with its functional equivalent that has been slightly modified ("implementation" RTL), helping design teams save considerable amounts of time and resources. Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code.
AI-Based Sequence Detection

Article - Mar 01, 2020 by Asif Ahmad, Abhishek Chauhan - Agnisys

In this era of automation, significant advantages can be gained by automatically generating verification and validation sequences from natural language text using artificial intelligence (AI) based sequence detection techniques, and then using those sequences in C/UVM code. This article talks about the current state of development in this area and gives ideas about how you can implement your own solution to achieve true specification-driven software development.
An Open Data Management Tool for Design and Verification

Article - Mar 01, 2020 by Vishal Patel, Manoj Pandey - Arastu Systems

The Big Data technology has evolved to handle both volume and velocity of data, currently being generated by the chip design and verification activities. The core challenge of effective data management and hence actionable insight generation is still not available to the industry in the true sense. Connecting data islands as created by various tools in various formats across digital design and verification workflows and creating a Unified Data Lake is an important missing piece.
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip

Article - Mar 01, 2020 by Dr. Nicole Fern - Tortuga Logic

Modern electronic systems are complex, and economics dictate that the design, manufacturing, testing, integration and deployment of Application Specific Integrated Circuits (ASICs), System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs) span companies and countries. Security and trust in this diverse landscape of 3rd party IP providers, processor vendors, SoC integrators and fabrication facilities, is both challenging and introduces security risks.
Formal Verification of RISC-V® Processors

Article - Mar 01, 2020 by Dr. Ashish Darbari

The verification of modern-day processors is a non-trivial exercise, and RISC-V® is no exception. In this article, we present a formal verification methodology for verifying a family of RISC-V® “low-power” processors. Our methodology is both new and unique in the way we address the challenges of verification going beyond just functional verification.
Tackling Random Blind Spots with Strategy-Driven Stimulus Generation

Article - Jan 07, 2020 by Matthew Ballance
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

Article - Jan 07, 2020 by Joe Hupcey
Low Power Coverage: The Missing Piece in Dynamic Simulation

Article - Jan 07, 2020 by Progyna Khondkar
Low Power Apps: Shaping the Future of Low Power Verification

Article - Jan 07, 2020 by Verification News
Managing and Automating HW/SW Tests from IP to SoC

Article - Jan 07, 2020 by Matthew Ballance
Reusable UPF: Transitioning from RTL to Gate Level Verification

Article - Jan 07, 2020 by Verification News
Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy

Article - Jan 07, 2020 by Matthew Ballance
Results Checking Strategies with Portable Stimulus

Article - Jan 07, 2020 by Matthew Ballance
Coverage Driven Verification of NVMe Using Questa VIP

Article - Jan 07, 2020 by Verification News
Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task

Article - Jan 07, 2020 by Charles Battikha
Technical Paper: Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task

Resource - Jan 07, 2020 by
Achieving Functional Safety for Autonomous Vehicle SoC Designs

Article - Dec 06, 2019 by Jake Wiltgen
Technical Paper: Achieving Functional Safety for Autonomous Vehicle SoC Designs

Resource - Dec 06, 2019 by
Why Hardware Emulation Is Necessary to Verify Deep Learning Designs

Article - Dec 03, 2019 by Jean-Marie Brunet

There is no doubt that computers have changed our lives forever. Still, as much as computers outperform humans at complex tasks such as solving complex mathematical equations in almost zero time, they may underperform when solving what humans can do easily — image identification, for instance. Anyone in the world can identify a picture of a cat in no time at all. The most powerful PC in the world may take hours to get the same answer.
Deadlock Prevention Made Easy with Formal Verification

Article - Dec 03, 2019 by Dr. Jeremy Levitt

You are about to go into a planning meeting for a new project when you get a call from one of your company’s Customer Advocate Managers: a product that you worked on just started shipping in volume, and there are a growing number of field reports that the system randomly freezes-up after a few weeks in operation. While a soft reset “works,” it will run anywhere from 5 to 10 days before it has to be rebooted again.
Exercising State Machines with Command Sequences

Article - Dec 03, 2019 by Matthew Ballance

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design.
Designing A Portable Stimulus Reuse Strategy

Article - Dec 03, 2019 by Matthew Ballance

The PSS language was designed with the requirements of test intent reuse, and automated test creation in mind. The requirement to allow test intent to be reused across a variety of very different platforms drove the PSS language to enable a clean and clear distinction between test intent and test realization, as shown in Figure 1. In a PSS description, test intent specifies the high-level view of what behavior is to be exercised.
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon

Article - Dec 03, 2019 by Kurt Takara

In this article, we will discuss the difficulties encountered with traditional CDC protocol verification methodologies and present a complete methodology to overcome the current challenges.