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I Didn’t Know Visualizer Could Do That

Webinar - Mar 30, 2021 by Rich Edelman

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
Preventing Glitch Nightmares on CDC Paths

Webinar - Mar 26, 2021 by Ping Yeung

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
Applying Big Data to Next-Generation Coverage Analysis and Closure

Webinar - Mar 26, 2021 by Darron May

In this session, we will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before.
The Life of a SystemVerilog Variable

Webinar - Mar 26, 2021 by Dave Rich

This session presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
Preventing Glitch Nightmares on CDC Paths

Resource (Slides (.PDF)) - Mar 26, 2021 by Ping Yeung

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
Bounded Proof Sign-Off with Formal Coverage

Resource (Paper (.PDF)) - Mar 26, 2021 by Joe Hupcey

In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
Applying Big Data to Next-Generation Coverage Analysis and Closure

Resource (Slides (.PDF)) - Mar 26, 2021 by Darron May

Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration.
Bounded Proof Sign-Off with Formal Coverage

Resource (Paper (.PDF)) - Mar 26, 2021 by Joe Hupcey

When using formal verification on large DUTs, after solving an initial set of provable assertions, it is common to have some remaining assertions which are not proven -- or disproven -- in the course of the analysis. Even though formal couldn’t conclusively verify the expected behavior, the DUT behaviors recorded up until the analysis halted still provides meaningful information.
The Life of a SystemVerilog Variable

Resource (Paper (.PDF)) - Mar 26, 2021 by Dave Rich

Some of the most common issues are how and when variables get initialized, how concurrent threads interact with the same variable, and how certain variable lifetimes interact with other SystemVerilog features in terms of performance considerations. This paper presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
The Life of a SystemVerilog Variable

Resource (Slides (.PDF)) - Mar 26, 2021 by Dave Rich

In software programming, lifetime is defined by when and from where a variable is available for access. This is particularly important when there are multiple process threads with lifetimes of their own trying to access the same variable. A variable becomes a symbolic name for a particular range of memory locations allocated to a specific data type.
Preventing Glitch Nightmares on CDC Paths: The Three Witches

Resource (Slides (.PDF)) - Mar 26, 2021 by
Preventing Glitch Nightmares on CDC Paths: The Three Witches

Resource (Paper (.PDF)) - Mar 26, 2021 by
ModelSim to Questa - Productivity Features

Webinar - Mar 25, 2021 by Jonathan Craft

In this session, you will gain an understanding of the differences between the ModelSim and Questa simulators and will be introduced to the advanced verification techniques and methodology necessary for design and verification of high-end FPGA and ASIC.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Webinar - Mar 25, 2021 by Ray Salemi

This session introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Resource (Slides (.PDF)) - Mar 25, 2021 by Ray Salemi

How does Python drive the simulator? One approach: cocotb
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Resource (Paper (.PDF)) - Mar 25, 2021 by Ray Salemi

This paper introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.
Spiral Refinement Methodology for Silicon Bug Hunt

Webinar - Mar 24, 2021 by Mark Eslinger

In this session, we capture the refinement process into a step-by-step methodology, formulate it graphically so that it is easy to understand and replicate.
Spiral Refinement Methodology for Silicon Bug Hunt

Resource (Paper (.PDF)) - Mar 24, 2021 by Ping Yeung

This paper will present a "spiral refinement" bug hunt methodology that captures the success factors and guides the deployment of various formal techniques. The objective is to identify the significant challenges and gradually improve each of the factors to "zero-in" on the critical bugs.
Spiral Refinement Methodology for Silicon Bug Hunt

Resource (Slides (.PDF)) - Mar 24, 2021 by Ping Yeung

Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification. It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently.
Advance your Designs with Advances in CDC and RDC

Resource (Slides (.PDF)) - Mar 23, 2021 by Kurt Takara

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC.
Advance your Designs with Advances in CDC and RDC

Webinar - Mar 23, 2021 by Kurt Takara

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC.
Cocotb Bus Functional Models

Resource (Verification Horizons Blog) - Mar 22, 2021 by Ray Salemi

How to use cocotb to write bus functional models in Python.
Automatic Formal Verification - Questa Static and Formal Apps

Webinar - Mar 21, 2021 by Walter Gude

In this session, you will gain an understanding of the automatic formal applications that can be used to solve current design and verification challenges.
Introduction to Coroutines

Resource (Verification Horizons Blog) - Mar 11, 2021 by Ray Salemi

Why a Python feature intended for I/O and asynchronous communication is perfect for verification.
Celebrating 10 Years of the UVM

Article - Mar 03, 2021 by Mark Peryer

Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.