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Scoreboard (28)
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Classes (27)
Introduction to UVM (27)
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ASIC (26)
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UVM Basics (24)
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Waveform (24)
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Cookbook (23)
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Assurance (22)
Design Optimization (22)
Formal Analysis (22)
Non-Trivial Bug Escapes (22)
Block Level (21)
Covergroup (21)
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PCI Express (21)
Synchronization (21)
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Acceleration (20)
Advanced UVM (20)
Driver (20)
FSM (20)
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U2U (20)
X-Tracing (20)
Constrained Random Verification (19)
Coverage Analysis (19)
Coverage Metrics (19)
Design Constructs (19)
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Interactive Mode (19)
Memory (19)
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Python (19)
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Abstraction (18)
Big Data (18)
C (18)
Code Generator (18)
Collaborative Analysis (18)
Coverage Points (18)
Netlist (18)
Packages (18)
Advanced Debug Techniques (17)
Asynchronous Clock (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Polymorphism (17)
Safety Mechanism (17)
State Space (17)
U2U Europe (17)
Arrays (16)
Automation (16)
Constrained Random Stimulus (16)
Controllers (16)
DFT (16)
Data Types (16)
Power States (16)
Sequence Driver (16)
Signal (16)
Testplan (16)
API (15)
Gate-Level (15)
Inconclusives (15)
QVIP Configurator (15)
Requirements Management (15)
Reset-Domain Checking (15)
Scenario Generation (15)
Sequence Item (15)
Testbench Automation (15)
VRM (15)
Variable (15)
Verification Practice (15)
Virtual Interface (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
BFMs (14)
COCOTB (14)
Config_db (14)
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Customization (14)
Failure Analysis (14)
Fault Simulation (14)
Interoperability (14)
March 2016 - Volume 12 Issue 1 (14)
Performance (14)
SLEC (14)
UVMC Kit (14)
Virtual Sequences (14)
Continuous Integration (13)
Expressions (13)
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Glitches (13)
Power Intent (13)
Python for Verification Series (13)
Sequencer (13)
System Level (13)
X-Propagation (13)
ASIL (12)
CDC Analysis (12)
DVCon Japan (12)
Declaration (12)
Environment Pattern (12)
HLS (12)
Intelligent Automation (12)
Monitors (12)
NVMe (12)
Parameterized Classes (12)
Productivity Gap (12)
Register Layer Adapter (12)
September 2021 - Volume 17 Issue 2 (12)
Unit Testing (12)
Universal Chiplet Interconnect Express (12)
Verification IQ (12)
Verification Run Manager (12)
AXI (11)
Adoption Trends (11)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Connections (11)
Creating and Using Constrained Random (11)
DFT Verification (11)
Gate-Level Simulation (11)
Generation (11)
Interview (11)
Jenkins (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
Operators (11)
PYUVM (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Sub-system (11)
Test Environment (11)
Tool Assessment (11)
UCIe (11)
Verification Process Overview (11)
osmosis 2025 (11)
Checkers (10)
Continuous Integration System (10)
Coverage Models (10)
Design Complexity (10)
Fault Analysis (10)
Fault Grading (10)
Hardware Acceleration (10)
Hierarchical Components (10)
Inheritance (10)
Interrupts (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Macros (10)
Model Checking (10)
Multi-Die (10)
Proof Coverage (10)
Property Debug (10)
Report (10)
Root of Trust (10)
Safety Metrics (10)
Stimulus Generation (10)
Unified Power Format (10)
VIQ (10)
Bitstream (9)
Breakpoint (9)
Chiplets (9)
Configuration Object (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
DPI-C (9)
Data Management (9)
Data Mining (9)
Data Models (9)
Data Types and Procedural Statements (9)
Deadlock (9)
Formal Assertion-Based Verification (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Monitor (9)
Multi-Core Architectures (9)
Predictive Analysis (9)
Reference Model (9)
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Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
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Training (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
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Whats New in Functional Verification (9)
1800.2 (8)
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Algorithms (8)
B/C/R Script (8)
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Class Handles (8)
Class Reference (8)
Clock Gating (8)
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Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
HDL Domain (8)
HTML Docs (8)
High Speed (8)
IC Reliability (8)
Interconnect (8)
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June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Matlab (8)
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Procedural Statements (8)
Randomization (8)
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Supply Set (8)
Timing (8)
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Verification Component (8)
osmosis 2023 A&D (8)
3DIC (7)
ADAS (7)
AI Algorithms (7)
Bind (7)
CDC Protocol (7)
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Class Objects (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
DAC 2019 (7)
Design Assurance (7)
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Error Injection (7)
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Execution Semantics and Synchronization (7)
IP Blocks (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
Iterations (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Metastable (7)
Migration (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Order Property Pattern (7)
Parallel Simulation (7)
Parameter (7)
Power Analysis (7)
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Power Logic (7)
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Predictors (7)
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Register Package (7)
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Structural Analysis (7)
System Scaling (7)
TLM FIFOS (7)
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Testbench Customization in UVM (7)
Tool Qualification (7)
Traceability (7)
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UCDB (7)
UCIe 2.0 (7)
VA Live 2023 - Huntsville (7)
Waivers (7)
X-Checking (7)
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AEH (6)
Agent (6)
Appendix (6)
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CDC Path (6)
Co-Simulation (6)
Coverage Intent (6)
DDR (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Mitigation (6)
Digital Design (6)
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Electronic Hardware (6)
HPC (6)
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High-Speed (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
November 2016 - Volume 12 Issue 3 (6)
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October 2012 - Volume 8 Issue 3 (6)
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Open Source (6)
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Reporting (6)
SPI (6)
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Slave (6)
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Strategy (6)
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UALink (6)
UVM Forum (6)
Utilization (6)
VA Live 2024 - El Segundo (6)
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VA Live 2025 - Hudson (6)
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Verbosity (6)
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Voltage Domain Crossing (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Analysis Pattern (5)
BIST (5)
Bus Protocol (5)
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Creating and Using a Test Plan (5)
DAC 2018 (5)
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DSP (5)
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December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
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Error (5)
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Flip-Flop (5)
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High-Level Synthesis (5)
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JEDEC (5)
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MARLUG 2024 (5)
March 2018 - Volume 14 Issue 1 (5)
Modules (5)
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Sub-system Level (5)
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VA Live 2019 - Westford (5)
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DisplayPort (4)
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ECO (4)
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ICE Mode (4)
IEEE (4)
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Non-Pipelined (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
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QoR (4)
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Register-Level Scoreboards (4)
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UART (4)
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VA Live 2023 - Austin (4)
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1.2 (3)
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July 2023 - Volume 19 Issue 2 (3)
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