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The New Leader in Verification IP: Questa + Avery Solutions

Resource (Slides (.PDF)) - Jun 06, 2023 by Gordon Allan

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the industry leader for Verification IP. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform

Resource (Slides (.PDF)) - Jun 06, 2023 by Moses Satyasekaran

During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities.
Transactional Assertions - Where representation influences thinking

Resource (Slides (.PDF)) - May 31, 2023 by Nicolae Tusinschi

In this session, you will learn about more about transactional assertions.
GapFree - Where all pieces come together

Resource (Slides (.PDF)) - May 31, 2023 by Nicolae Tusinschi

In this session, you will learn how OneSpin joining Siemens EDA creates a compelling combination by providing a comprehensive, best-in-class, accessible Formal solution.
Break the RISC-V customization barrier with Processor Formal Verification

Resource (Slides (.PDF)) - May 31, 2023 by Salaheddin Hetalani

In this session, you will learn the challenges of processor verification and how the RISC-V community recognizes the need for stronger verification.
When Regular CDC Is Not Enough: Reset Domain Crossing Verification and Hierarchical Data Modeling (HDM)

Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell

In this session, you will learn more about RDC and how to accelerate your CDC with hierarchical data models.
A multi-dimensional view of formal verification coverage

Resource (Slides (.PDF)) - May 31, 2023 by Nicolae Tusinschi

In this session, you will learn more about formal coverage and verification coverage integration advantages.
Advanced CDC flows: Dynamic Metastability Modeling, Protocol Verification, Reconvergence

Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell

In this session, you will learn more how dynamic CDC addresses static CDC limitations, and how to benefit from CDC transfer protocols and structural reconvergence verification.
Enhancing CDC flows with Machine Learning (ML) today, and the future roadmap of static solutions

Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell

In this session, you will learn why Siemens EDA is investing in the power of machine learning (ML) in static & formal verification to increase efficiency and confidence.
osmosis Aerospace and Defense 2023

Conference - May 30, 2023 by Martin Rowe

osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

Resource (Verification Horizons Blog) - May 24, 2023 by Rich Edelman

I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this year – and anyhow, my wife is the gardener in the house. But it’s my job to do some weeding. While meditative, it is disagreeable to me. But back to UVM Debug and Visualizer.
Efficient Interconnect Formal Verification for Complex, Large-scale Designs

Webinar - May 17, 2023 by Nicolae Tusinschi

In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
Efficient Interconnect Formal Verification for Complex, Large-scale Designs

Resource (Slides (.PDF)) - May 17, 2023 by Nicolae Tusinschi

In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
Delivering First Silicon Success for Your Next SoC or 3DIC

Resource (Slides (.PDF)) - Apr 25, 2023 by Gordon Allan

Now that our acquisition of Avery Design Systems is complete, Siemens EDA are the new leaders in Verification IP in the industry. Our combined team of experts are ready to provide the industry with a complete protocol and memory verification portfolio, to bring independent, high-quality verification, standards-based solutions that are interoperable across all simulators, and quality which is already trusted by the most successful silicon teams across the globe.
Delivering First Silicon Success for Your Next SoC or 3DIC

Webinar - Apr 25, 2023 by Gordon Allan

In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.
Groups of Class Specializations in SystemVerilog

Resource (Verification Horizons Blog) - Apr 25, 2023 by Chris Spear

In a previous post , I said that in SystemVerilog, once you specialize a class, you can not make a group of them. Oops! Turns out that UVM does this all this time. You just need to know where to start. Just to be clear, you are making a group of handles, an array. Every object is separate, and thus cannot organized into an array.
Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Webinar - Apr 11, 2023 by Darron May

In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.
Back to the Future with Formal Property Checking (PDF)

Resource - Apr 03, 2023 by
The Digital Twin: An Aerospace and Defense Revolution

Session - Mar 29, 2023 by Ray Salemi

This session will provide a look into a seamless and comprehensive Digital Thread for Defense and the immense value it brings.
Continuous Integration (CI) Driving Efficient Program Execution

Webinar - Mar 28, 2023 by Kevin Campbell

In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
Continuous Integration (CI) driving efficient program execution

Resource (Slides (.PDF)) - Mar 28, 2023 by Kevin Campbell

In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

Webinar - Mar 18, 2023 by Joon Hong

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Webinar - Mar 16, 2023 by Neil Johnson

In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.
Introduction to SystemVerilog Assertions

Webinar - Mar 15, 2023 by Chris Crile

In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.
Rapid Testbench Development

Resource (Slides (.PDF)) - Mar 07, 2023 by Bob Oden

Slides covering the UVM Framework, system model refinement and automated testbench creation.