New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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SIEMENS Verification Academy

Questa CDC-FX: Metastability Effects Delay Modeling

This paper describes why metastability occurs in designs with
asynchronous clocks and analyzes the various methods that designers use to verify that their design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in the Siemens EDA Questa clock-domain-crossing verification solution.

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