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UVM - Universal Verification Methodology (448)
Formal Verification (294)
Planning, Measurement and Analysis (142)
Verification IP (136)
Functional Safety (126)
Standards (110)
UVM Framework (86)
Debug (85)
SystemVerilog (68)
Simulation (67)
Low Power (64)
Clock-Domain Crossing (61)
Coverage (58)
Questa Design Solutions (49)
FPGA Verification (46)
UVMC (45)
Acceleration (44)
Machine Learning (43)
Portable Stimulus (36)
Analog Mixed-Signal (31)
Verification IQ (29)
Reset-Domain Crossing (25)
Verification Academy Live (24)
Verification Management (19)
Assertions (18)
Python (14)
VHDL 2008 (11)
High-Level Synthesis (9)
Design For Test (4)
UVM (552)
SystemVerilog (409)
Testbench (315)
Formal Verification (300)
Verification Horizons (275)
Debug (156)
Standards (145)
Verification IP (141)
Coverage (133)
DVCon (125)
Protocol (121)
Aerospace (118)
Mil/Aero (118)
Sequences (112)
RTL (104)
Low Power (96)
UVMF (94)
Functional Safety (93)
Assertions (91)
UVM Framework (91)
Simulation (90)
UPF (89)
AI/ML (88)
CDC (88)
Clock-Domain Crossing (87)
Verification Management (87)
FPGA (79)
Functional Verification (77)
Stimulus (75)
Transactions (72)
Verification Planning (72)
Power Aware (71)
ISO 26262 (70)
QDS (68)
Components (67)
FPGA Verification (66)
Analysis (65)
DUT-TB (64)
Machine Learning (64)
Automotive (61)
Constraints (61)
Metrics (61)
SystemC (60)
Coverage Closure (59)
RDC (57)
Emulation (56)
Methodology (56)
Functional Coverage (55)
Registers (54)
Code Example (52)
HW/SW Verification (52)
Property Checking (52)
Generative AI (51)
Tests (51)
Verification Process (50)
Industry Trends (49)
Wilson Research Group (49)
Reuse (48)
FPGA Designs (47)
Integrated Environment (47)
Regression (47)
Safety Critical (47)
Interfaces (46)
UVM Connect (46)
Verification Environment (46)
Verification Trends (46)
SoC (45)
Verification Productivity (45)
Portable Test & Stimulus (44)
UVMC (44)
VHDL (43)
Avery Verification IP (41)
Formal Apps (41)
Formal Coverage (40)
Trends (39)
Compliance (38)
Emerging Trends (38)
OOP (38)
RISC-V (38)
Security Verification (38)
DAC (36)
Equivalence Checking (36)
Formal Analysis (36)
PSS (36)
Artificial Intelligence (35)
IEEE 1801 (35)
Power Management (35)
TLM 2.0 (35)
Configuration (34)
Connectivity (34)
IC/ASIC (34)
Questa One (34)
Verification Efficiency (34)
AMS (33)
Factory (33)
Objects (33)
Power Domain (33)
WRG (33)
Code Coverage (32)
Scoreboard (32)
ASIC (31)
DO-254 (31)
Reset-Domain Crossing (31)
Bug Hunting (30)
Metastability (30)
Modeling (30)
TLM (30)
osmosis 2022 (30)
Accellera (29)
CDC Methodology (29)
PCIe (29)
Properties (29)
Register Model (29)
Reset Issues (29)
Safety Analysis (29)
Classes (28)
Design Optimization (28)
Safety Architecture (28)
Test Planning (28)
UVM Debug (28)
Introduction to UVM (27)
Lint (27)
Patterns (27)
Requirements Traceability (27)
Synchronization (27)
Verilog (27)
Analytics (26)
Block Level (26)
Coverage Analysis (26)
Coverage Metrics (26)
Functional Simulation (26)
Property Checks (26)
Waveform (26)
Abstraction (25)
Archive (25)
Requirements (25)
Asynchronous Clock (24)
Cookbook (24)
Design Trends (24)
Driver (24)
Fault Campaign (24)
Lifecycle (24)
Netlist (24)
Object Oriented Programming (24)
Performance (24)
Testplan (24)
UVM Basics (24)
Co-Emulation (23)
FSM (23)
System Level (23)
osmosis 2024 (23)
Assurance (22)
Collaborative Analysis (22)
Data-driven Verification (22)
Memory (22)
Non-Trivial Bug Escapes (22)
Proofs (22)
VRM (22)
Verification Closure (22)
Arrays (21)
Big Data (21)
Chiplets (21)
Config_db (21)
Constrained Random Verification (21)
Covergroup (21)
Interactive Mode (21)
Interoperability (21)
PCI Express (21)
Packages (21)
U2U (21)
osmosis 2023 (21)
Acceleration (20)
Advanced UVM (20)
C (20)
Constrained Random Stimulus (20)
Continuous Integration (20)
Data Types (20)
Design Constructs (20)
Functional Verification Study (20)
Hardware Fault (20)
Python (20)
Signal (20)
X-Tracing (20)
DFT (19)
Power States (19)
Requirements Management (19)
Safety Mechanism (19)
Safety Workflow (19)
Scenario Generation (19)
Verification Practice (19)
Verification Run Manager (19)
Virtual Interface (19)
API (18)
Advanced Debug Techniques (18)
Automation (18)
Code Generator (18)
Configuration Database (18)
Controllers (18)
Coverage Points (18)
Polymorphism (18)
Sequence Item (18)
Sequencer (18)
State Space (18)
CDC Analysis (17)
Design Complexity (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Sequence Driver (17)
Testbench Automation (17)
U2U Europe (17)
UCIe (17)
Virtual Sequences (17)
BFMs (16)
Gate-Level (16)
HLS (16)
Reset-Domain Checking (16)
SLEC (16)
Universal Chiplet Interconnect Express (16)
Class Objects (15)
Continuous Integration System (15)
DFT Verification (15)
Data Models (15)
Expressions (15)
Inconclusives (15)
Intelligent Automation (15)
Power Intent (15)
QVIP Configurator (15)
Sub-system (15)
Variable (15)
osmosis Europe 2025 (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Customization (14)
FPGA Prototyping (14)
Failure Analysis (14)
Fault Simulation (14)
Glitches (14)
IC Reliability (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
NVMe (14)
Productivity Gap (14)
Register Layer Adapter (14)
Stimulus Generation (14)
UVMC Kit (14)
AXI (13)
Checkers (13)
Data Mining (13)
Declaration (13)
Formal Application (13)
Functional Correctness (13)
Gate-Level Simulation (13)
Hardware Acceleration (13)
Interconnect (13)
Multi-Die (13)
Operators (13)
Python for Verification Series (13)
RDC Analysis (13)
Validation (13)
Verification IQ (13)
X-Propagation (13)
ASIL (12)
Adoption Trends (12)
Agent (12)
Co-Simulation (12)
Coverage Models (12)
DVCon Japan (12)
Environment Pattern (12)
Hierarchical Components (12)
Interrupts (12)
Iterations (12)
Parameterized Classes (12)
Predictive Analysis (12)
Randomization (12)
September 2021 - Volume 17 Issue 2 (12)
Strategy (12)
Tool Assessment (12)
Traceability (12)
Unit Testing (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Configuration Object (11)
Connections (11)
Convergence (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DPI-C (11)
Fault Grading (11)
Generation (11)
High Speed (11)
Interview (11)
Isolation (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
PYUVM (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Test Environment (11)
VIQ (11)
Verification Process Overview (11)
3DIC (10)
AMBA (10)
Backdoor Accesses (10)
Breakpoint (10)
Class Handles (10)
Class Reference (10)
Command API (10)
Data Management (10)
Deadlock (10)
FPU (10)
Fault Analysis (10)
High-Level Synthesis (10)
Implementation Model (10)
Inheritance (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Metrics-Driven (10)
Model Checking (10)
Parallel Simulation (10)
Proof Coverage (10)
Property Debug (10)
RDC Methodology (10)
Report (10)
Reset Architecture (10)
Root of Trust (10)
SVA (10)
Safety Metrics (10)
Scalable Verification (10)
Timing (10)
Unified Power Format (10)
Verification Architecture (10)
Verification Component (10)
osmosis 2025 (10)
1800.2 (9)
AI Algorithms (9)
Bitstream (9)
CDC Path (9)
CDC Protocol (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
Data Types and Procedural Statements (9)
Encapsulation (9)
Formal Assertion-Based Verification (9)
HPC (9)
Hardware Security (9)
Hierarchical Sequences (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Metastable (9)
Multi-Core Architectures (9)
PSL (9)
Parameter (9)
Power Analysis (9)
Power Logic (9)
Power Optimization (9)
RDC Violations (9)
Reconvergence (9)
Reference Model (9)
Retention (9)
SPI (9)
Schematic (9)
Secure Data Path (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Sub-system Level (9)
Testbench Architecture (9)
Testing Strategies (9)
Training (9)
UALink (9)
UCDB (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Waivers (9)
Whats New in Functional Verification (9)
Algorithms (8)
B/C/R Script (8)
Clock Gating (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
Floating-Point Units (8)
HDL Domain (8)
HTML Docs (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Mixed-Signal Design (8)
OSCI (8)
OVM2UVM (8)
Occurrence Property Pattern (8)
Overrides (8)
Phasing (8)
Pipelined (8)
Postsim (8)
Procedural Statements (8)
Release (8)
Reporting (8)
Reset Tree (8)
Safety (8)
Simulation Coverage (8)
State Machine (8)
State Transitions (8)
Supply Set (8)
System Scaling (8)
UCIe 2.0 (8)
UVM Verification (8)
Voltage Domain Crossing (8)
osmosis 2023 A&D (8)
ADAS (7)
Agentic AI (7)
Bind (7)
Bounded Proof (7)
Cache Coherency (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
Data Transfer (7)
Design Assurance (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
Fork-Join (7)
Guidelines (7)
IP Blocks (7)
IP Integration (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
Layering (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Modules (7)
Monitor (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Objections (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Power Estimation (7)
Predictors (7)
Property Analysis (7)
Safety Verification (7)
Schematic Debug (7)
Sequential Analysis (7)
Siemens EDA (7)
Specification (7)
Static & Formal Adoption (7)
Static Checks (7)
Structural Analysis (7)
Supply Network (7)
TLM FIFOS (7)
Technology Scaling (7)
Test Generation (7)
Test Verification (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
Transaction Recording (7)
VA Live 2023 - Huntsville (7)
Verification Complete (7)
X-Checking (7)
X-Corruption (7)
XML (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Bug Detection (6)
Computational Storage (6)
Corner-case Bugs (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
DDR (6)
Debug Methodology (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Constraints (6)
Design Mitigation (6)
Design Patterns (6)
Digital Design (6)
Digital Twin (6)
Distributed Resource Management (6)
Electronic Hardware (6)
Fabric (6)
Flip-Flop (6)
Front and Back Door (6)
HDL (6)
HDM (6)
Hardware Designs (6)
Hierarchical Flow (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PCIe Gen 7 (6)
Power Efficiency (6)
Pre-Silicon (6)
Prototyping (6)
Random Faults (6)
Respins (6)
Slave (6)
Transaction-Level (6)
UCIe 3.0 (6)
UVM Forum (6)
UVVM (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
VHDL Testbench (6)
Verbosity (6)
Verification Effectiveness (6)
Visualization (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bus Functional Models (5)
Bus Protocol (5)
CHERI (5)
Callbacks (5)
Class Library (5)
Class Types (5)
Clock Propagation (5)
Co-Verification (5)
Concurrent Processes (5)
Constraint Solver (5)
Converters (5)
Coverage Holes (5)
DAC 2024 (5)
DSP (5)
Data Encryption (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Dual Domains (5)
Error (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Formal Testbench (5)
HBM4 (5)
Hardware Verification (5)
Hierarchical Data Model (5)
High-Speed (5)
IDE (5)
Implicit/Explicit (5)
In-Circuit Emulation (5)
JEDEC (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
March 2018 - Volume 14 Issue 1 (5)
Memory Usage (5)
NVM Express (5)
Namespaces (5)
Post-silicon Debug (5)
Precedence (5)
Processor Core Verification (5)
Quirky (5)
Repository (5)
SSD (5)
SVUnit (5)
Sequence Library (5)
Simulink (5)
Spice (5)
Split Transactor (5)
State-Based Model (5)
Static Analyses (5)
Static RDC (5)
Stimulus Pattern (5)
Tessent Test Solutions (5)
Test Class (5)
Threads (5)
Transaction-Based Acceleration (5)
VA Live 2019 - Westford (5)
VA Live 2023 - Westford (5)
VA Live 2024 - Huntsville (5)
VA Live 2024 - Westford (5)
VA Live 2025 - Silicon Valley (5)
VA Live 2026 - El Segundo (5)
Verbose (5)
Virtual Methods (5)
Wishbone (5)
5G (4)
AI Model (4)
Bandwidth (4)
Batch and Debug (4)
Bi-Directional (4)
Bins (4)
Bit Width (4)
Black Boxing (4)
Bounded Model Checking (4)
C++ (4)
CXL (4)
Checkpoint (4)
Compute Subsystems (4)
Coverage Achievement (4)
DVFS (4)
Data Link (4)
Deprecated (4)
Design Analysis (4)
Design Hierarchy (4)
Determinism (4)
Development Environment (4)
DisplayPort (4)
Driver Tracing (4)
Dynamic Power (4)
ECO (4)
ED-80 (4)
Enumeration (4)
Fault List (4)
Formal Closure (4)
Formal Methods (4)
HBM (4)
HDMI (4)
Hardware-Assisted Verification (4)
ICE Mode (4)
IEEE (4)
Implementation Driven Formal (4)
Implementation Pattern (4)
In-Circuit Simulation (4)
In-System Test (4)
Initial States (4)
Instance (4)
LFM (4)
Large Language Models (4)
Low Latency (4)
Mathworks (4)
Metastability Injection (4)
Mitigation Architecture (4)
Non-Pipelined (4)
Non-Reset (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
Partitioning (4)
Phase Objections (4)
Phases (4)
Plusargs (4)
Protocol Checkers (4)
QEMU (4)
QoR (4)
Questa Design Solutions (4)
RTL Sign-Off (4)
Race Conditions (4)
Register-Level Scoreboards (4)
Reset Handling (4)
Reset Signal (4)
Risk Mitigation (4)
Root Cause (4)
SVTB (4)
Specification Pattern (4)
Subscriber (4)
Subsystem (4)
Synergistic Verification (4)
Syntax (4)
Tcl/Tk (4)
Test Ranking (4)
Time Cone (4)
UART (4)
UEC (4)
UPF 4.0 (4)
USB (4)
Unified Coverage Database (4)
Unreachability (4)
Use Models (4)
Utilization (4)
VA Live 2023 - Austin (4)
VA Live 2024 - Austin (4)
VA Live 2024 - Fremont (4)
VA Live 2025 - Scottsdale (4)
VA Live 2026 - Austin (4)
VA Live 2026 - Silicon Valley (4)
Vectors (4)
Verification Models (4)
Verification Success (4)
X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
Affect Probability (3)
Airborne Electronic Hardware (3)
Analysis Components (3)
Analysis Port (3)
Application Lifecycle Management (3)
Arbitration (3)
Autonomous Systems (3)
BISR (3)
Base Test (3)
Bidirectional Protocols (3)
Boolean (3)
Built-In Self-Test (3)
CDC Signals (3)
CSI-2 (3)
Case Statements (3)
Cause-Effect (3)
Certification (3)
Class Variables (3)
Classifications (3)
Clocking (3)
Code Quality (3)
Control Logic (3)
Coroutines (3)
Cover Method (3)
Coverage Exclusion (3)
Cryptography (3)
Data Processing (3)
Delay Loops (3)
Design Cycle (3)
Design Flow (3)
Design Specification (3)
Design for Safety (3)
Domain Specific Architectures (3)
Dual Top (3)
ESL (3)
Emulatability (3)
Exhaustive (3)
FWHW (3)
Fault Detection (3)
Fibre Channel (3)
Formal Verification Apps (3)
Golden Model (3)
HLV (3)
Handles (3)
Hardware Architecture (3)
Hardware Assurance (3)
Horizontal Reuse (3)
IC Design (3)
Integrity Challenges (3)
Intelligent Integration (3)
JUnit (3)
July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
LRM (3)
Level-shifter (3)
Load Balancing (3)
Loggers (3)
MC2 (3)
Mailboxes (3)
Mathematical Analysis (3)
Memory Debug (3)
NRRs (3)
NoC (3)
OSVVM (3)
Objectives (3)
Observer (3)
Open Architecture (3)
PCI-SIG (3)
PHY (3)
Parallel Compile (3)
Parallel Computing (3)
Phase-Level (3)
Polymorphic Behavior (3)
Power Architecture (3)
Power Gating (3)
Profiling (3)
Protocol Layers (3)
QFL (3)
Qrun (3)
Quality Assurance (3)
RISC-V Verification Interface (3)
RTL Emulation (3)
Radiation Mitigation (3)
Re-Spins (3)
Re-targeting (3)
Real Number Modeling (3)
Reconfiguration (3)
Register Assistant (3)
Register-Level Stimulus (3)
Resource Utilization (3)
Routines (3)
Safety Assurance (3)
Security Coverage (3)
Security Vulnerabilities (3)
Semantics (3)
Semaphores (3)
Semiconductor (3)
Sequential Optimization (3)
Serial Interface (3)
Shift Left (3)
Singleton (3)
Slave Agent (3)
Source Code Management (3)
Specification Driven Formal (3)
Spiral Refinement (3)
State Transition (3)
Static Lists (3)
Static Properties (3)
Stream (3)
TBX (3)
TDISP (3)
Test Coverage (3)
Test Realization (3)
Transfer Protocols (3)
Transitive (3)
Trust Verification (3)
Type Casting (3)
UEFI (3)
UVM 1.1d (3)
UVM 1.2 (3)
UVM Rapid Adoption (3)
UVMC 2.3.0 (3)
UVMC 2.3.1 (3)
UVMC 2.3.2 (3)
UVMC 2.3.3 (3)
UVMC 2.3.4 (3)
Unidirectional (3)
Unreachable Code (3)
VHDL-2019 (3)
VIP - 3.1 (3)
VbyOne (3)
Verification Cycles (3)
Verification Framework (3)
Virtual Prototyping (3)
Virtual Sequencers (3)
X-State (3)
2D/3D (2)
AHB-Lite (2)
ALU (2)
APB (2)
ARBM (2)
ASIL-C (2)
Abstract Class (2)
Abstract Specification (2)
Abstract Stimulus (2)
Access Path (2)
Adaptive (2)
Agentic Workflow (2)
Arithmetic (2)
Assist (2)
Attribute (2)
AutoPDU (2)
Autonomous Vehicles (2)
BiQuad (2)
Bidirectional (2)
Bit Flips (2)
Bounded Tasks (2)
Bus Master (2)
C Tests (2)
C-PHY (2)
CDC Violations (2)
CDC Working Group (2)
CHI (2)
CSI (2)
Campaign Management (2)
Chains (2)
Channel Detection (2)
Clock Bridge (2)
Clock Cycle (2)
Clock Definitions (2)
Clock Detection (2)
Command Line Processor (2)
Concrete Class (2)
Context-Aware Debug (2)
Controllability (2)
Core Services (2)
Cost Benefit (2)
Cover Capabilities (2)
Cover Properties (2)
Cover Statement (2)
Coverage Data (2)
Critical Storage (2)
Cross Probing (2)
Cutpoint (2)
D-PHY (2)
DPPM (2)
DVCON 2021 (2)
DVCon India (2)
Data Mux (2)
Design Checking (2)
Design Configuration (2)
Design Creation (2)
Designers (2)
Digital Signal Processing (2)
Domain Configuration (2)
Domain Topologies (2)
Downcasting (2)
ECUs (2)
ENV Package (2)
Elements List (2)
Embedded Software (2)
Enterprise Debug and Analysis (2)
Existence (2)
FIT Rate (2)
Facial Recognition (2)
False Path (2)
Fault Coverage (2)
Fault Model (2)
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2223 Results

  • Verifying Chiplet Interconnects at Scale: UCIe® 3.0

    Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez

    This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon. Guest Presenter: Jie Ding – Ayar Labs

  • Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters

    Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta

    This session highlights the importance of UALink and the verification challenges it introduces and shows how Avery UALink Verification IP delivers immediate value by accelerating bring-up, improving coverage of protocol corner cases, and reducing overall verification risk and time-to-market. Guest Presenter: Saro Kalinagasamy – Astera Labs

  • Achieving Mathematical Certainty in Design Verification with Formal

    Paper - Jan 31, 2026 by Nicolae Tusinschi

    This paper provides a comprehensive exploration of formal verification methodologies, techniques, and best practices for hardware design engineers and verification specialists. Formal verification employs mathematical analysis to prove correctness across all possible scenarios. This exhaustive approach is particularly critical in safety-critical systems, high-reliability applications, and complex digital designs where corner-case bugs can have catastrophic consequences.

  • Achieving Mathematical Certainty in Design Verification with Formal

    Resource (Paper (.PDF)) - Jan 31, 2026 by Nicolae Tusinschi

    The future of hardware verification lies in the intelligent combination of formal verification, simulation, and other verification methodologies, each applied where it provides the most value. By mastering the techniques presented in this whitepaper, verification engineers position themselves to meet the verification challenges of increasingly complex hardware designs.

  • Supercharge Your CDC & RDC Analysis with the Power of AI/ML

    Webinar - Jan 28, 2026 by Farhad Ahmed

    One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.

  • Supercharge Your CDC & RDC Analysis with the Power of AI/ML

    Resource (Slides (.PDF)) - Jan 28, 2026 by Farhad Ahmed

    In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.

  • Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

    Webinar - Jan 21, 2026 by Sunil Sahoo

    This webinar will delve into  Questa One Sim’s groundbreaking metastability injection capability , a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic.

  • Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

    Resource (Slides (.PDF)) - Jan 21, 2026 by Sunil Sahoo

    In this webinar, you will learn how to gain unparalleled confidence in your design’s resilience to metastability effects, ensuring robust functional correctness and accelerating verification closure for complex multi-clock SoCs.

  • BUGGED OUT Podcast

    Podcast - Jan 20, 2026 by Harry Foster

    Every chip has bugs — the real question is how fast you can find and fix them. BUGGED OUT is the bite-sized podcast where we shine a light on the art (and science) of functional verification.

  • New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

    Resource (Paper (.PDF)) - Jan 16, 2026 by Jin Hou

    The heterogeneous integration of multiple ICs in a single package along with high-performance, high bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections.

  • New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

    Paper - Jan 16, 2026 by Jin Hou

    This paper introduces a new way to functionally verify packaging connectivity using formal verification that can exhaustively verify all interconnections between IC blocks. The flow is automatic for all steps, from creating connectivity specifications to verifying packaging output connectivity. The automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. The script for the flow is simple and only takes a few minutes to set up.

  • Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

    Webinar - Jan 14, 2026 by Abdelrahman Tharwat

    In this webinar, we’re excited to showcase the latest cutting-edge features of Questa One Sim, with UVVM (Universal VHDL Verification Methodology) . Learn how the newly added support for constrained randomization with multi-variable capabilities allows you to dynamically generate randomized, UVVM-compliant stimuli that address even the most intricate design constraints, helping you explore vast verification scenarios efficiently and effectively.

  • Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

    Resource (Slides (.PDF)) - Jan 14, 2026 by Abdelrahman Tharwat

    This webinar is your gateway to unlocking a streamlined and enhanced verification experience by leveraging Questa One Sim advanced features in tandem with UVVM.

  • System Verifier

    Resource (Verification Horizons Blog) - Jan 05, 2026 by Julie Weber

    Software-defined, AI-controlled systems are transforming industries—from aerospace and defense to automotive and industrial automation. But with this transformation comes complexity: as software workloads grow, electronic systems face higher risks of non-deterministic failure mechanisms. Traditional engineering methods and tools are no longer enough to anticipate these risks or prevent “integration hell.”

  • Formal Verification of Synthesizable C++/SystemC Designs

    Resource (Paper (.PDF)) - Dec 12, 2025 by Vlada Kalinic

    In this paper, you will learn that HLV formal tools from Siemens can be used to clean SystemC/C++ design code before running HLS as well as to verify the functionality of the SystemC designs with SVA assertions. Steps in this flow include using the GUI counter-example capability to debug failures on the SystemC/C++ designs and focusing on the reachable parts by using the increase coverage solution to detect unreachable code.

  • Formal Verification of Synthesizable C++/SystemC Designs

    Paper - Dec 12, 2025 by Vlada Kalinic

    Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL.

  • The Future of Semiconductors: Engineering in the Convergence Era

    Resource (Paper (.PDF)) - Dec 09, 2025 by Harry Foster

    The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.

  • The Future of Semiconductors: Engineering in the Convergence Era

    Paper - Dec 09, 2025 by Harry Foster

    Reflections from inside an industry undergoing its biggest transformation in decades. The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.

  • FutureCast 2026: A Special Holiday Edition of BUGGED OUT

    Resource (Verification Horizons Blog) - Dec 09, 2025 by Harry Foster

    As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is accelerating faster than many expected. Chip architectures are evolving, system boundaries are shifting, and verification continues expanding into new territory we couldn’t have imagined even a decade ago. And like many of you, I find the end of the year to be a natural time to pause, look back, and ask a simple but important question: Where is all of this heading?

  • Aerospace & Defense

    Reference - Dec 03, 2025 by Todd Holbrook

    Welcome to the Aerospace and Defense event archive, where you will find presentations and slide decks from live events that you may have missed. *Please note: you will need a valid login to download the session presentations.

  • Questa One Smart Verification: Unleashing the Potential of AI Within Functional Verification

    Resource (Slides (.PDF)) - Dec 03, 2025 by Austin Mam

    Leverage the power of AI and ML Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.

  • Introducing Questa One SFV: The Transformation of Static & Formal Powered by AI/ML

    Resource (Slides (.PDF)) - Dec 03, 2025 by David Landoll

    In today's fast-paced development schedules, engineers are constantly balancing innovation with efficiency. Questa One SFV, powered by AI/ML, is designed to streamline workflows, eliminate steep learning curves, and accelerate adoption. Learn how SFV can integrate into your current flow and improve productivity.

  • Ensure High Quality RTL with Early Continuous Integration

    Resource (Slides (.PDF)) - Dec 03, 2025 by Walter Gude

    Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.

  • Enhancing Verification Productivity with Questa One

    Resource (Slides (.PDF)) - Dec 03, 2025 by Sunil Sahoo

    Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance— it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. Questa One Sim's productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.

  • VA Live - Scottsdale: Introduction and Welcome

    Resource (Slides (.PDF)) - Dec 03, 2025 by Todd Holbrook

    Welcome to Verification Academy Live.