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UVM - Universal Verification Methodology (448)
Formal Verification (293)
Planning, Measurement and Analysis (141)
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ISO 26262 (69)
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Introduction to UVM (27)
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Driver (24)
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Netlist (24)
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Testplan (24)
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Non-Trivial Bug Escapes (22)
Performance (22)
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System Level (22)
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Covergroup (21)
Interactive Mode (21)
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Memory (21)
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Packages (21)
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Acceleration (20)
Advanced UVM (20)
C (20)
Chiplets (20)
Constrained Random Stimulus (20)
Data Types (20)
Design Constructs (20)
Functional Verification Study (20)
Hardware Fault (20)
Python (20)
Signal (20)
X-Tracing (20)
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DFT (19)
Power States (19)
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API (18)
Advanced Debug Techniques (18)
Automation (18)
Code Generator (18)
Configuration Database (18)
Controllers (18)
Coverage Points (18)
Polymorphism (18)
Sequence Item (18)
Sequencer (18)
State Space (18)
CDC Analysis (17)
Design Complexity (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Sequence Driver (17)
Testbench Automation (17)
U2U Europe (17)
UCIe (17)
Virtual Sequences (17)
BFMs (16)
Gate-Level (16)
HLS (16)
Reset-Domain Checking (16)
SLEC (16)
Universal Chiplet Interconnect Express (16)
Class Objects (15)
Continuous Integration System (15)
Data Models (15)
Expressions (15)
Inconclusives (15)
Intelligent Automation (15)
Power Intent (15)
QVIP Configurator (15)
Sub-system (15)
Variable (15)
osmosis Europe 2025 (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Customization (14)
DFT Verification (14)
FPGA Prototyping (14)
Failure Analysis (14)
Fault Simulation (14)
Glitches (14)
IC Reliability (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
NVMe (14)
Productivity Gap (14)
Register Layer Adapter (14)
Stimulus Generation (14)
UVMC Kit (14)
AXI (13)
Checkers (13)
Declaration (13)
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Functional Correctness (13)
Gate-Level Simulation (13)
Hardware Acceleration (13)
Interconnect (13)
Multi-Die (13)
Operators (13)
Python for Verification Series (13)
RDC Analysis (13)
Verification IQ (13)
X-Propagation (13)
ASIL (12)
Adoption Trends (12)
Agent (12)
Co-Simulation (12)
Coverage Models (12)
DVCon Japan (12)
Data Mining (12)
Environment Pattern (12)
Hierarchical Components (12)
Interrupts (12)
Iterations (12)
Parameterized Classes (12)
Randomization (12)
September 2021 - Volume 17 Issue 2 (12)
Strategy (12)
Tool Assessment (12)
Traceability (12)
Unit Testing (12)
Validation (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Configuration Object (11)
Connections (11)
Convergence (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DPI-C (11)
Fault Grading (11)
Generation (11)
High Speed (11)
Interview (11)
Isolation (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
PYUVM (11)
Predictive Analysis (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Test Environment (11)
VIQ (11)
Verification Process Overview (11)
AMBA (10)
Backdoor Accesses (10)
Breakpoint (10)
Class Handles (10)
Class Reference (10)
Command API (10)
Deadlock (10)
FPU (10)
Fault Analysis (10)
High-Level Synthesis (10)
Implementation Model (10)
Inheritance (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Metrics-Driven (10)
Model Checking (10)
Parallel Simulation (10)
Proof Coverage (10)
Property Debug (10)
RDC Methodology (10)
Report (10)
Reset Architecture (10)
Root of Trust (10)
SVA (10)
Safety Metrics (10)
Timing (10)
Unified Power Format (10)
Verification Architecture (10)
Verification Component (10)
osmosis 2025 (10)
1800.2 (9)
3DIC (9)
AI Algorithms (9)
Bitstream (9)
CDC Path (9)
CDC Protocol (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
Data Management (9)
Data Types and Procedural Statements (9)
Encapsulation (9)
Formal Assertion-Based Verification (9)
HPC (9)
Hardware Security (9)
Hierarchical Sequences (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Metastable (9)
Multi-Core Architectures (9)
PSL (9)
Parameter (9)
Power Analysis (9)
Power Logic (9)
Power Optimization (9)
RDC Violations (9)
Reconvergence (9)
Reference Model (9)
Retention (9)
SPI (9)
Scalable Verification (9)
Schematic (9)
Secure Data Path (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Testbench Architecture (9)
Testing Strategies (9)
Training (9)
UALink (9)
UCDB (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Waivers (9)
Whats New in Functional Verification (9)
Algorithms (8)
B/C/R Script (8)
Clock Gating (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
Floating-Point Units (8)
HDL Domain (8)
HTML Docs (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Mixed-Signal Design (8)
Monitor (8)
OSCI (8)
OVM2UVM (8)
Occurrence Property Pattern (8)
Overrides (8)
Phasing (8)
Pipelined (8)
Postsim (8)
Procedural Statements (8)
Release (8)
Reporting (8)
Reset Tree (8)
Safety (8)
Simulation Coverage (8)
State Machine (8)
State Transitions (8)
Sub-system Level (8)
Supply Set (8)
System Scaling (8)
UCIe 2.0 (8)
UVM Verification (8)
Voltage Domain Crossing (8)
osmosis 2023 A&D (8)
ADAS (7)
Agentic AI (7)
Bind (7)
Bounded Proof (7)
Cache Coherency (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
Data Transfer (7)
Design Assurance (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
Fork-Join (7)
Guidelines (7)
IP Blocks (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
Layering (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Modules (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Objections (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Power Estimation (7)
Predictors (7)
Property Analysis (7)
Safety Verification (7)
Schematic Debug (7)
Sequential Analysis (7)
Siemens EDA (7)
Specification (7)
Static Checks (7)
Structural Analysis (7)
Supply Network (7)
TLM FIFOS (7)
Technology Scaling (7)
Test Generation (7)
Test Verification (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
Transaction Recording (7)
VA Live 2023 - Huntsville (7)
Verification Complete (7)
X-Checking (7)
X-Corruption (7)
XML (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Bug Detection (6)
Computational Storage (6)
Corner-case Bugs (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
DDR (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Constraints (6)
Design Mitigation (6)
Design Patterns (6)
Digital Design (6)
Distributed Resource Management (6)
Electronic Hardware (6)
Fabric (6)
Flip-Flop (6)
Front and Back Door (6)
HDL (6)
HDM (6)
Hardware Designs (6)
Hierarchical Flow (6)
IP Integration (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PCIe Gen 7 (6)
Power Efficiency (6)
Pre-Silicon (6)
Random Faults (6)
Respins (6)
Slave (6)
Static & Formal Adoption (6)
Transaction-Level (6)
UCIe 3.0 (6)
UVM Forum (6)
UVVM (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
VHDL Testbench (6)
Verbosity (6)
Verification Effectiveness (6)
Visualization (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bus Functional Models (5)
Bus Protocol (5)
CHERI (5)
Callbacks (5)
Class Library (5)
Class Types (5)
Clock Propagation (5)
Co-Verification (5)
Concurrent Processes (5)
Constraint Solver (5)
Converters (5)
Coverage Holes (5)
DAC 2024 (5)
DSP (5)
Data Encryption (5)
Debug Methodology (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Digital Twin (5)
Dual Domains (5)
Error (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Formal Testbench (5)
HBM4 (5)
Hierarchical Data Model (5)
High-Speed (5)
IDE (5)
Implicit/Explicit (5)
In-Circuit Emulation (5)
JEDEC (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
March 2018 - Volume 14 Issue 1 (5)
Memory Usage (5)
NVM Express (5)
Namespaces (5)
Post-silicon Debug (5)
Precedence (5)
Processor Core Verification (5)
Prototyping (5)
Quirky (5)
Repository (5)
SSD (5)
SVUnit (5)
Sequence Library (5)
Simulink (5)
Spice (5)
Split Transactor (5)
State-Based Model (5)
Static Analyses (5)
Static RDC (5)
Stimulus Pattern (5)
Test Class (5)
Threads (5)
Transaction-Based Acceleration (5)
VA Live 2019 - Westford (5)
VA Live 2023 - Westford (5)
VA Live 2024 - Huntsville (5)
VA Live 2024 - Westford (5)
VA Live 2025 - Silicon Valley (5)
Verbose (5)
Virtual Methods (5)
Wishbone (5)
5G (4)
AI Model (4)
Bandwidth (4)
Batch and Debug (4)
Bi-Directional (4)
Bins (4)
Bit Width (4)
Black Boxing (4)
Bounded Model Checking (4)
C++ (4)
CXL (4)
Checkpoint (4)
Coverage Achievement (4)
DVFS (4)
Data Link (4)
Deprecated (4)
Design Analysis (4)
Design Hierarchy (4)
Determinism (4)
DisplayPort (4)
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Dynamic Power (4)
ECO (4)
ED-80 (4)
Enumeration (4)
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Formal Closure (4)
Formal Methods (4)
HBM (4)
HDMI (4)
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IEEE (4)
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Initial States (4)
Instance (4)
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Large Language Models (4)
Low Latency (4)
Mathworks (4)
Metastability Injection (4)
Mitigation Architecture (4)
Non-Pipelined (4)
Non-Reset (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
Partitioning (4)
Phase Objections (4)
Phases (4)
Plusargs (4)
Protocol Checkers (4)
QoR (4)
Questa Design Solutions (4)
Race Conditions (4)
Register-Level Scoreboards (4)
Reset Handling (4)
Reset Signal (4)
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Root Cause (4)
SVTB (4)
Specification Pattern (4)
Subscriber (4)
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Syntax (4)
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Test Ranking (4)
Time Cone (4)
UART (4)
UEC (4)
UPF 4.0 (4)
USB (4)
Unified Coverage Database (4)
Unreachability (4)
Use Models (4)
Utilization (4)
VA Live 2023 - Austin (4)
VA Live 2024 - Austin (4)
VA Live 2024 - Fremont (4)
VA Live 2025 - Scottsdale (4)
VA Live 2026 - Silicon Valley (4)
Vectors (4)
Verification Models (4)
Verification Success (4)
X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
Affect Probability (3)
Airborne Electronic Hardware (3)
Analysis Components (3)
Analysis Port (3)
Application Lifecycle Management (3)
Arbitration (3)
Autonomous Systems (3)
BISR (3)
Base Test (3)
Bidirectional Protocols (3)
Boolean (3)
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CDC Signals (3)
CSI-2 (3)
Case Statements (3)
Cause-Effect (3)
Certification (3)
Class Variables (3)
Classifications (3)
Clocking (3)
Code Quality (3)
Control Logic (3)
Coroutines (3)
Cover Method (3)
Coverage Exclusion (3)
Cryptography (3)
Data Processing (3)
Delay Loops (3)
Design Cycle (3)
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Design Specification (3)
Design for Safety (3)
Development Environment (3)
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ESL (3)
Emulatability (3)
Exhaustive (3)
FWHW (3)
Fault Detection (3)
Fibre Channel (3)
Formal Verification Apps (3)
Golden Model (3)
HLV (3)
Handles (3)
Hardware Architecture (3)
Hardware Assurance (3)
Hardware Verification (3)
Horizontal Reuse (3)
IC Design (3)
Integrity Challenges (3)
Intelligent Integration (3)
JUnit (3)
July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
LRM (3)
Level-shifter (3)
Load Balancing (3)
Loggers (3)
MC2 (3)
Mailboxes (3)
Mathematical Analysis (3)
Memory Debug (3)
NRRs (3)
NoC (3)
OSVVM (3)
Objectives (3)
Observer (3)
Open Architecture (3)
PCI-SIG (3)
PHY (3)
Parallel Compile (3)
Parallel Computing (3)
Phase-Level (3)
Polymorphic Behavior (3)
Power Architecture (3)
Power Gating (3)
Profiling (3)
Protocol Layers (3)
QEMU (3)
QFL (3)
Qrun (3)
Quality Assurance (3)
RISC-V Verification Interface (3)
RTL Emulation (3)
RTL Sign-Off (3)
Radiation Mitigation (3)
Re-Spins (3)
Re-targeting (3)
Real Number Modeling (3)
Reconfiguration (3)
Register Assistant (3)
Register-Level Stimulus (3)
Resource Utilization (3)
Routines (3)
Safety Assurance (3)
Security Coverage (3)
Security Vulnerabilities (3)
Semantics (3)
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Semiconductor (3)
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Static Lists (3)
Static Properties (3)
Stream (3)
TBX (3)
TDISP (3)
Test Coverage (3)
Test Realization (3)
Transfer Protocols (3)
Transitive (3)
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Type Casting (3)
UVM 1.1d (3)
UVM 1.2 (3)
UVM Rapid Adoption (3)
UVMC 2.3.0 (3)
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VHDL-2019 (3)
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Assist (2)
Attribute (2)
AutoPDU (2)
BiQuad (2)
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Bounded Tasks (2)
Bus Master (2)
C Tests (2)
C-PHY (2)
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CDC Working Group (2)
CHI (2)
CSI (2)
Campaign Management (2)
Chains (2)
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Clock Bridge (2)
Clock Cycle (2)
Clock Definitions (2)
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Command Line Processor (2)
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Concrete Class (2)
Context-Aware Debug (2)
Controllability (2)
Core Services (2)
Cost Benefit (2)
Cover Capabilities (2)
Cover Properties (2)
Cover Statement (2)
Coverage Data (2)
Critical Storage (2)
Cross Probing (2)
Cutpoint (2)
D-PHY (2)
DPPM (2)
DVCON 2021 (2)
DVCon India (2)
Data Mux (2)
Design Checking (2)
Design Configuration (2)
Design Creation (2)
Designers (2)
Digital Signal Processing (2)
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ECUs (2)
ENV Package (2)
Elements List (2)
Embedded Software (2)
Enterprise Debug and Analysis (2)
Existence (2)
FIT Rate (2)
Facial Recognition (2)
False Path (2)
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2212 Results

  • Accelerated Confidence in Interface Designs Mixing Software Layers, Hardware Protocols, Physical Connections

    Conference - Jun 24, 2024 by Gordon Allan

    In this session, you will learn that today high performance compute fabrics are spread over multiple die, multiple packages, multiple cards and racks in the data center. They are linked together by layers of CPU-to-CPU, cache-to-cache, and network node-to-node infrastructure. Those connections are based on standardized protocols, always evolving and improving, and increasingly having both a hardware interaction of multiple layers, plus one or more software layers.

  • Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove

    Conference - Jun 24, 2024 by Tom Fitzpatrick

    In this session, you will learn that the Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviors that will execute, the test can easily be retargeted to different implementations for different environments.

  • Challenges of Developing IPs for AI Chips

    Conference - Jun 24, 2024 by Tom Fitzpatrick

    Tom Fitzpatrick interviews Rambus VP of Engineering Susheel Tadikonda about the high-level D&V challenges of developing IPs for the new breed of AI accelerator chips; including the need to support a high-degree of IP configurability, 3DIC-specific protocol requirements that call for new levels of security for data in-motion and at rest.

  • VA Live - Huntsville: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • VA Live - San Diego: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • VA Live - El Segundo: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • VA Live - Westford: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • Learn about the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

    Resource (Verification Horizons Blog) - Jun 04, 2024 by Joe Hupcey

    The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle to keep up with the latest enhancements and capabilities. Hence, the “PCI SIG” standards organization holds an annual conference for D&V engineers to learn directly from the industry’s PCIe experts via technical training sessions; sharing best practices to ultimately improve product roll-out and interoperability.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Resource (Slides (.PDF)) - Jun 04, 2024 by Rick Schmidt - Siemens EDA

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • Mark your calendar for the 2024 DAC-Chips to Systems Conference

    Resource (Verification Horizons Blog) - May 28, 2024 by Harry Foster

    Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.

  • Questa RDC Assist: Accelerate Reset Closure with AI/ML

    Webinar - May 22, 2024 by Farhad Ahmed

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    Resource (Slides (.PDF)) - May 22, 2024 by Farhad Ahmed

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification

    Resource (Slides (.PDF)) - May 21, 2024 by Chris Giles

    Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

  • Functional Monitoring: From Lab to In-Life

    Resource (Slides (.PDF)) - May 21, 2024 by Fady Abushahla - Siemens EDA

    In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.

  • Navigating Reset Domain Crossings to Safety in Complex SoCs

    Resource (Verification Horizons Blog) - May 21, 2024 by Reetika - Siemens EDA

    As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management blocks, and DSP cores are proliferating. This surge necessitates a shift towards intricate power and performance management strategies, often incorporating several asynchronous and soft resets.

  • Beyond Speed: Unlocking Productivity in Simulation and Debug

    Resource (Slides (.PDF)) - May 21, 2024 by Moses Satyasekaran

    Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

    Resource (Slides (.PDF)) - May 21, 2024 by Austin Mam

    This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Resource (Slides (.PDF)) - May 21, 2024 by Kamlesh Mulchandani

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • From Chaos to Order: Using Continuous Integration for Hardware Functional Verification

    Paper - May 13, 2024 by Dr. Abdelouahab Ayari

    In recent years, continuous integration and development have become crucial in organizing software development cycles. As a result, it has also become a way to streamline hardware flow, especially with the increased complexity of chips and SoCs. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.

  • From Chaos to Order: Using Continuous Integration for Hardware Functional Verification

    Resource (Paper (.PDF)) - May 13, 2024 by Dr. Abdelouahab Ayari

    Continuous integration plays an important role in organizing the hardware flow and making integration seamless, easy, and trackable using the ability of running multiple jobs in parallel it is capable of accelerating the workflow. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.

  • Without Objection: Touring the uvm_objection Implementation - Uses and Improvements

    Resource (Paper (.PDF)) - May 13, 2024 by Rich Edelman

    This paper will explain uvm_objections implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.

  • Without Objection: Touring the uvm_objection Implementation - Uses and Improvements

    Paper - May 13, 2024 by Rich Edelman

    The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that “isn't done yet.” For example, an objection can prevent a process from finishing until some other process agrees. uvm_objections are sometimes overused and are always misunderstood. This paper will explain the implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.

  • On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

    Paper - May 10, 2024 by Farhad Ahmed

    Reset tree checks should be viewed thoroughly before RDC analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction.

  • On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

    Resource (Paper (.PDF)) - May 10, 2024 by Farhad Ahmed

    This paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.

  • Developing “Safe” AI Hardware

    Conference - May 07, 2024 by Shaumik Ganguly - Continental

    In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.