Challenges of Multiple FPGA Tool Flow Verification

This session will examine the challenges of utilizing common RTL for different FPGA targets. Each FPGA target requires a different tool flow, therefore verification of each tool flow is necessary in determining functional accuracy. Traditionally, functional verification has been sufficient to guard against tool flow issues. Functional safety requirements necessitate a more robust verification process. Equivalency checking ensures that a tool flow defect is not realized in the final product.