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Beyond Speed: Unlocking Productivity in Simulation and Debug

Resource (Slides (.PDF)) - May 21, 2024 by Moses Satyasekaran

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.
Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

Resource (Slides (.PDF)) - May 21, 2024 by Austin Mam

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.
The New Leader in Verification IP: Questa + Avery Solutions

Resource (Slides (.PDF)) - May 21, 2024 by Kamlesh Mulchandani

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
Developing “Safe” AI Hardware

Conference - May 07, 2024 by Shaumik Ganguly - Continental

In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.
Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Conference - May 07, 2024 by Suma Ramanand - Nokia

In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.
Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

Conference - May 07, 2024 by Ariel Ansbacher - Veriest

In this session you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.
Extraction of VC File for Physical Macro From Top VC File

Conference - May 07, 2024 by Nirav Patel - Arm

A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.
Improving Simulation Performance Utilizing the Visualizer Profiler

Conference - May 07, 2024 by George Lloyd - Arm

In this session you will learn how Visualizer Profiler was used to identify areas for improvement within Arm VIP components and how these issues were addressed, reducing simulation time that were achieved due to these optimizations.
Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches

Conference - May 07, 2024 by Espen Tallaksen - EmLogic

In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).
Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend

Conference - May 07, 2024 by Mihajlo Katona - Veriest

In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method.
New AI Horizons in Static & Formal Verification

Resource (Recording) - Apr 24, 2024 by Dan Yu
New AI Horizons in Static & Formal Verification

Resource (Slides (.PDF)) - Apr 24, 2024 by Dan Yu
Optimizing FPGA Equivalence Checking for A&D Designs

Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Urish
Driving Efficient Execution with Continuous Integration

Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Campbell
Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

Resource (Slides (.PDF)) - Apr 24, 2024 by Dr. Jonathan Graf
osmosis Aerospace and Defense 2024

Conference - Apr 24, 2024 by John Hallman

osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Resource (Slides (.PDF)) - Apr 16, 2024 by Rich Edelman

In this webinar we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size.
Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Webinar - Apr 16, 2024 by Rich Edelman

Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.
Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

Conference - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA

It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.
Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

Resource (Slides (.PDF)) - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA

It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.
Why and How We Migrated from In-house Regression Management and Coverage Flow to Verification IQ

Conference - Apr 04, 2024 by Avinash Agrawal - Siemens EDA

In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ

Resource (Slides (.PDF)) - Apr 04, 2024 by Avinash Agrawal - Siemens EDA

In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
How and Why We Adopted Questa Core in the Development of Quantum Computers

Conference - Apr 04, 2024 by Jan Marjanovic - Atom Computing

This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.
How and Why We Adopted Questa Core in the Development of Quantum Computers

Resource (Slides (.PDF)) - Apr 04, 2024 by Jan Marjanovic - Atom Computing

This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.
How We Use PCIe Verification IP Across Multiple Projects

Conference - Apr 04, 2024 by Weiping Guo - Marvell

In this session we will discuss how Marvell delivers successful products and drives the market by with a structured design and verification methodology that reflects this philosophy. Specifically, we will dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP.