Verification Academy

Topic	Replies	Views	Activity
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	1	429	July 5, 2024
System Verilog Threads SystemVerilog disable-fork	7	113	January 22, 2025
Task execution not blocked when invoked in fork join_none SystemVerilog SystemVerilog , fork-join_none-multiple-threads , systemverilog-uvm	7	265	August 12, 2024
Concurrent assertion checking the condition even when clk is not high SystemVerilog assertion , Assertion-system-verilog	7	157	December 10, 2024
Write a constraint to generate the pattern 1234554321 SystemVerilog SystemVerilog , systemverilog-constraint	3	353	November 25, 2024
Constraint for 101 pattern SystemVerilog SystemVerilog , constraint-randomization	6	141	May 13, 2025
Approaches for the following Assertion SystemVerilog assertion , SVA	4	201	September 26, 2024
Magic square constraint SystemVerilog	5	139	December 12, 2024
Assertion to check weather a clock toggles or not SystemVerilog assertion	7	145	February 3, 2025
SVA help needed SystemVerilog assertion	7	202	July 18, 2024
Unsupported Index type for an associative array in an interactive constraint SystemVerilog constraint-randomization , associative-array	5	146	December 16, 2024
Constraint to have sum of elements in an array = 100 SystemVerilog constraint-randomization	4	153	January 28, 2025
Need help in writing assertion SystemVerilog assertion	7	189	October 14, 2024
How to shuffle a 2D array in systemverilog? SystemVerilog constraint-randomization	4	255	November 6, 2024
Constraint question SystemVerilog constraint-randomization	1	252	July 30, 2024
Can anyone please me to generate below constraint SystemVerilog UVM	1	349	July 17, 2024
System verilog constraint SystemVerilog	4	131	January 9, 2025
Virtual sequence UVM	4	173	August 30, 2024
Assertion coding for a random pattern SystemVerilog assertion	5	126	March 1, 2025
Can anyone suggest how to write following assertion SystemVerilog assertion , SVA	5	134	February 22, 2025
Constraint Dynamic Array SystemVerilog systemverilog-constraint , Array	7	154	December 5, 2024
Suggestions for +uvm_set_verbosity UVM UVM , uvm_set_verbosity	5	482	September 18, 2024
Values injection into randomize variable SystemVerilog SystemVerilog , constraints	8	246	September 2, 2024
Best practice to align interfaces in UVM testbench UVM UVM	6	114	November 14, 2024
Calling two sequencer from one sequence UVM sequencer , sequence	3	151	December 27, 2024
Assertion without using clock SystemVerilog assertion	3	205	September 25, 2024
Coverpoint bins for fractional values SystemVerilog UVM , Coverage	4	121	December 14, 2024
Develop 5 threads by using threads concept and make sure if any of 3 threads are completed out of 5 threads then kill other 2 threads SystemVerilog SystemVerilog , thread , for-loop-fork-join_none , fork-join_any , fork , disable-fork , fork-join , fork_join , threads , thread-fork	5	135	March 18, 2025
Popping Queue elements as sequence_expr SystemVerilog SystemVerilog , assertion , SVA-Assertion	7	227	November 2, 2024
Sva paper: dynamic data structures in assertions Announcements	0	50	October 30, 2024
How to Run Both Parent and Child sequence_item in a UVM Test? UVM UVM	6	129	January 6, 2025
Does a wait statement in a test main phase block the main phase execution of other testbench component's phases? UVM phase , wait-statement , phasing	4	203	July 3, 2024
System verilog constraint associative array SystemVerilog constraint-randomization	2	275	September 17, 2024
Randomizing 2D int arrays producing unexpected results SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	2	256	July 11, 2024
Surjective mapping constraint SystemVerilog SystemVerilog , constraint-randomization	5	109	January 22, 2025
Uvm_event with parameter UVM SystemVerilog	7	188	February 17, 2025
AXI, Out of order SystemVerilog axi-amba-protocol	1	280	December 16, 2024
How to connect a single DUT port to multiple interface signals? UVM SystemVerilog	3	119	February 4, 2025
Procedural concurrent assertions within for loop SystemVerilog SystemVerilog , assertion , SVA	4	146	February 25, 2025
SV Constraint with Permutations and Combinations SystemVerilog	4	173	November 25, 2024
How to generate multiple cyclic random number? SystemVerilog	7	119	December 9, 2024
Sequence Stop or Kill UVM SystemVerilog , UVM	3	372	July 29, 2024
Column sum constraint for an 2D array SystemVerilog constraint , constraint-randomization , 2D-array-SystemVerilog-randomization	5	128	March 8, 2025
Can we extend sequencer and driver from uvm_component? UVM	5	215	August 12, 2024
[Interview Question] You have multiple analysis ports in your environment, and you need to broadcast a packet to all ports. How can you implement this in UVM? Write the relevant code snippet UVM	2	173	December 4, 2024
Correction Required in UVM Cookbook – Object vs. Component Override Explanation UVM UVM	4	92	April 4, 2025
Basic questions about the relationship between the sequence, the driver and the scoreboard UVM	4	116	January 30, 2025
First_match operator SystemVerilog assertion , first_match	4	236	August 27, 2024
Functional Coverage for AXI interconnect Coverage	1	350	May 29, 2025
Writing functions in Covergroup Coverage	1	474	May 7, 2025