Verification Academy

Topic	Replies	Views	Activity
SV Proability Constraint for Number of Set Bits SystemVerilog	4	346	January 16, 2024
UVM Verification project ideas UVM	3	284	February 25, 2024
Assertion to check for signal propagation SystemVerilog assertion	8	412	January 15, 2024
Constraint Interview Question SystemVerilog constraint-randomization	7	559	January 23, 2024
Constraint Question : Write a constraint for 2D Array where value of an element should be different from its neighbor SystemVerilog constraint-randomization	5	419	January 15, 2024
Constraint to Generate 10 bit number with set bits such that no set bits are together SystemVerilog constraint-randomization	7	302	February 17, 2024
Interview question on assertion Downloads Downloads	0	408	July 8, 2023
Coverpoint for dist Coverage SystemVerilog , Coverage , System-Verilog	1	270	January 2, 2024
How we can use task as function and function as task? SystemVerilog	1	69	April 3, 2024
Interview Question on UVM UVM	4	126	April 8, 2024
3 unique arrays - constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	1	123	April 3, 2024
Constraint for walking pattern (walking 1's) SystemVerilog systemverilog-constraint , uvm-sv-constraints	7	163	April 19, 2024
2D Array Column Sum Constraint Failing SystemVerilog constraint-randomization , systemverilog-constraint	3	355	January 16, 2024
Constraint to Generate Deck of 52 Cards SystemVerilog constraint-randomization , Constraint-Interview-Question	4	350	January 23, 2024
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	642	April 23, 2024
What is the advantage or the main purpose of using Followed by operator in SVA? SystemVerilog assertion , operators , SVA-Assertion-Systemverilog	4	197	January 14, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	85	April 7, 2024
SV Constraint :: Address must be aligned to the size of the transfer SystemVerilog SystemVerilog , constraint , constraint-randomization	7	206	March 14, 2024
Expression coverage Coverage Coverage	4	206	February 21, 2024
What is the difference between using #10 and ##10 inside initial block? SystemVerilog SystemVerilog , delays	2	221	January 16, 2024
SV Constraint Question SystemVerilog SystemVerilog , constraint-randomization	1	519	July 7, 2023
Systemverilog constraints SystemVerilog constraint-randomization , systemverilog-constraint	5	366	January 16, 2024
There are 2 agents. can Monitor from agent A communicate with Sequencer of Agent B. If yes how? UVM UVM , testbench	3	183	February 28, 2024
How to kill fork join if some of the threads ae finished SystemVerilog	1	82	April 25, 2024
Race condition of delay statement inside procedural code SystemVerilog	1	228	January 16, 2024
How to call the C testcase, for SOC verification UVM UVM	6	477	January 6, 2024
Using std::randomize SystemVerilog SystemVerilog , constraint-randomization	4	194	February 14, 2024
Constraints failure SystemVerilog constraint-randomization	2	73	March 29, 2024
Inheritance of clock for sequence used as event control SystemVerilog SystemVerilog , System-Verilog , SVA	4	198	January 16, 2024
Regarding const'() cast SystemVerilog SystemVerilog , Regarding-const-cast	5	433	January 10, 2024
What are some examples of protocol checking in monitor? UVM	3	254	January 16, 2024
Waveform for this assertion SystemVerilog SystemVerilog	5	341	December 20, 2023
How to abort from execution of an asynchronous timeout property? SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	3	185	January 15, 2024
Divide an array into two arrays SystemVerilog	6	341	January 9, 2024
Is there any way to set a global solve...before? SystemVerilog SystemVerilog , constraint , solve-before	1	85	April 3, 2024
Scoreboard for 2x2 router UVM	5	121	April 2, 2024
How to write a checker for this kind of DUT SystemVerilog	5	175	January 10, 2024
SVA assertion to check condition is satisfied until one signal asserted SystemVerilog	8	174	February 13, 2024
Solve before constraint used with implication operator SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	7	110	April 6, 2024
Constraint for 4 Queens Problem SystemVerilog	3	126	April 12, 2024
Raise_objection/ drop_obejction UVM UVM	2	132	February 13, 2024
Generate 200mz clock from 100mhz clock SystemVerilog	4	50	May 7, 2024
Constraint to generate values divisible by 5 in ascending order SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint , ascending-order-constraint , divisible-by-5	7	678	July 21, 2023
Write a constraint that assigns data to any address sequence that follows an arithmetic progression (ex: 1,5,9,13,17.. so a[1]=30, a[5]=30, a[9]=30 and so on)) SystemVerilog constraint , constraint-randomization , systemverilog-constraint	5	121	April 21, 2024
Using property expression ( a[0] ##1 b[0] ) \|=> c SystemVerilog SystemVerilog , assertion , SVA	5	248	January 3, 2024
SV Interfaces: best coding style to encapsulate functionality? SystemVerilog SystemVerilog , Interfaces	8	1051	October 12, 2023
How to get(access) the data members(properties) of sequencer from driver? UVM UVM	6	126	January 10, 2024
Regarding UVM Factory Macros UVM	4	179	January 17, 2024
Leetcode style website for verification engineers? SystemVerilog	4	238	January 10, 2024
Arbiter Req and Grant SystemVerilog assertion	4	252	January 3, 2024