Verification Academy

Topic	Replies	Views	Activity
Same base sequence for both virtual and original sequence UVM	6	123	August 26, 2025
Configuring agent in Active / Passive mode UVM uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	184	February 22, 2026
I need to know how many UVM active/Passive agents are required UVM UVM	4	104	April 4, 2026
Overriding Class properties SystemVerilog class , Polymorphism , virtual , virtual-polymorphism	6	162	September 18, 2025
Invoking response_handler even after seq_h.start completes UVM Response-Handler	4	149	August 8, 2025
Clock Frequency Verification SystemVerilog	1	141	July 10, 2025
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	132	January 17, 2026
What are different types of temporal Operators in SystemVerilog SystemVerilog SystemVerilog , assertion	3	190	September 29, 2025
SV Assertions using $past() SystemVerilog SystemVerilog , assertion	2	131	February 18, 2026
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	147	December 22, 2025
Disable scoreboard based on transactions UVM UVMF	1	162	August 1, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	182	October 21, 2025
Weighted constraints not working SystemVerilog constraint-randomization	3	107	January 2, 2026
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	155	November 11, 2025
Code debug help UVM	2	112	November 5, 2025
Multiple dist constraints SystemVerilog SystemVerilog , constraint-dist , systemverilog-distribution-constraints	5	117	April 27, 2026
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	5	140	October 12, 2025
Clock oscillator for testbench SystemVerilog	3	149	July 27, 2025
SVA sampling of always( a ##1 b[->1] ) SystemVerilog SystemVerilog , concurrent-assertion , Embdedded-Concurrent-assertion , always-property	6	81	February 8, 2026
Write method as task UVM	6	136	October 8, 2025
Usage of local:: keyword SystemVerilog SystemVerilog , systemverilog-constraint	6	186	September 19, 2025
Not operator used with [*] SystemVerilog assertion	1	153	July 14, 2025
Questions on constraint Distribution SystemVerilog SystemVerilog , dist , constraint-dist , systemverilog-distribution-constraints	3	108	April 22, 2026
Requesting clarity on constraint solving SystemVerilog constraint-randomization	2	135	January 7, 2026
Driver with DUT's output UVM driver	2	141	August 20, 2025
Parameterized DUT and Parameterized Interface UVM	2	131	July 13, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	109	July 2, 2025
Accessing invalid address is not working SystemVerilog	6	89	July 28, 2025
UVMF array agent UVM UVMF	0	166	August 3, 2025
Assertion failure using strong property SystemVerilog SVA , Sva-strong , strong-property , fail-action-block	7	112	February 19, 2026
Restrictions on fork join_any / join_none SystemVerilog fork-join_any-fork-join_none	1	148	December 10, 2025
Purpose of wait fork SystemVerilog	1	156	July 24, 2025
SV assertion related to req and grant SystemVerilog	2	137	October 18, 2025
Agent to agent communication UVM UVM	2	117	August 18, 2025
Uvm_resource_db UVM	1	120	July 5, 2025
Size() vs $size for constraining Unpacked Arrays SystemVerilog SystemVerilog , unpacked-array , arraysize , sizearray	4	76	April 14, 2026
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	101	November 2, 2025
Weird Message Verbosity Control by set_report_id_verbosity/_verbosity_level(_hier) UVM verbosity , UVM_VERBOSITY , UVM-Reporting , set_report_id_verbosity , set_report_verbosity_level	4	109	August 22, 2025
Dynamically building bins with don't care Coverage	4	166	August 15, 2025
Working of $monitor SystemVerilog monitor , monitor-SV-System-Function	5	80	February 17, 2026
Need help understanding formal verification of asynchronous FIFO SystemVerilog assertion , System-Verilog , SVA , Formal-Verification	1	132	April 15, 2026
Single uvm_analysis_port with multiple sequence items UVM UVM-TLM-Analysis-port	1	140	June 30, 2025
Display uvm_info including ps values UVM	7	101	November 23, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	138	October 21, 2025
How are registers supposed to deal with resets in UVM 2020? UVM uvm_reg , reset	6	88	February 3, 2026
Connection using modports with different signals SystemVerilog SystemVerilog , modport , interface	6	83	December 12, 2025
Clarification on sequence execution flow UVM cookbook figure UVM	6	117	October 16, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	109	October 2, 2025
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	120	March 10, 2026
Possible alternative to multiple $test$plusargs SystemVerilog SystemVerilog	2	155	July 15, 2025