Verification Academy

Topic	Replies	Views	Activity
Why create method is not part of uvm_object_wrapper? UVM uvm-factory	3	153	July 10, 2026
Question regarding the generate block SystemVerilog SystemVerilog	8	132	March 31, 2026
Working of $monitor SystemVerilog monitor , monitor-SV-System-Function	5	149	February 17, 2026
Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor? UVM UVM	3	127	June 23, 2026
Determining the bit width of operands in constraint SystemVerilog constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression	4	144	July 1, 2026
SV Assertions using $past() SystemVerilog SystemVerilog , assertion	2	179	February 18, 2026
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	157	November 2, 2025
Delay in update of mirrored value in explicit prediction UVM RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR	7	148	October 8, 2025
The question of disable SystemVerilog	6	117	July 13, 2026
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	4	170	September 22, 2026
Clarification on sequence execution flow UVM cookbook figure UVM	6	167	October 16, 2025
Requesting clarity on constraint solving SystemVerilog constraint-randomization	2	182	January 7, 2026
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	189	November 11, 2025
Questions on constraint Distribution SystemVerilog SystemVerilog , dist , constraint-dist , systemverilog-distribution-constraints	3	154	April 22, 2026
Suggestions for constraint on pattern occurrence SystemVerilog constraint-randomization , constraint-dist , systemverilog-distribution-constraints	3	148	April 9, 2026
Adding and deleting elements of dynamic type at same time SystemVerilog SystemVerilog , Queues , Dynamic-Array	2	151	November 29, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	218	October 21, 2025
SV assertion related to req and grant SystemVerilog	2	178	October 18, 2025
Updating UVM Component properties via Field Automation Macros UVM apply_config_settings , field-macros , UVM-field-macros , superbuild_phase	7	137	October 8, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	179	October 21, 2025
What are the biggest pain points in simulation debugging for DV engineers? UVM SystemVerilog	2	138	July 1, 2026
Need help understanding formal verification of asynchronous FIFO SystemVerilog assertion , System-Verilog , SVA , Formal-Verification	1	200	April 15, 2026
Uvm_hdl_read gives Incorrect value UVM	3	204	January 4, 2026
Code debug help UVM	2	138	November 5, 2025
Question on UVM Phases UVM UVM , UVM-phases , uvm_phases	1	179	July 24, 2026
implement a reference counter UVM UVM	3	97	June 25, 2026
Use of lock() method UVM	3	130	June 9, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	165	March 10, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? UVM SystemVerilog , UVM	2	188	February 18, 2026
Migrating from IP to sub-system level UVM	2	161	November 2, 2025
Restrictions on fork join_any / join_none SystemVerilog fork-join_any-fork-join_none	1	195	December 10, 2025
User-defined verbosity using uvm_config_db UVM	3	123	March 30, 2026
assertion to detect a specific switch of a signal SystemVerilog assertion	3	127	March 6, 2026
Unclear scheduling semantics for a flip-flop model with assign/deassign SystemVerilog SystemVerilog	4	88	June 27, 2026
Questions about the usage of Pattern Matching Conditional Statements SystemVerilog	3	103	July 6, 2026
Upward references in bound interfaces SystemVerilog	5	167	March 3, 2026
NULL mailbox error SystemVerilog	5	144	September 26, 2025
Backdoor Read consumes simulation time UVM RAL , UVM_BACKDOOR , uvm_ral	2	217	October 8, 2025
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM UVM	3	120	June 8, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	129	January 5, 2026
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	136	October 15, 2025
Cannot pass struct through uvm_config_db UVM uvm-config_db	3	139	October 3, 2025
Stable pwrite until pready SystemVerilog assertion	4	117	April 24, 2026
Default value of enumarated varaible is first value of enum SystemVerilog	4	122	November 1, 2025
Full_case parallel_case concrete explanation needed SystemVerilog Case-statement-in-sv	2	134	January 12, 2026
Scoreboard evaluating before monitor updates in SystemVerilog testbench (DFF) SystemVerilog	1	140	January 29, 2026
Calculating probability for solve x,y before z SystemVerilog SystemVerilog , constraint-randomization , randomization , solve-before	3	148	May 22, 2026
Iterator index querying example clarification SystemVerilog	4	110	December 14, 2025
Why Is Scoreboard Kept Separate from Agent in UVM? UVM UVM	2	124	June 3, 2026
Displaying associative array elements in Specific order SystemVerilog accessing-the-associative-array-elements , associative-array-methods , associative_arrays	2	122	December 18, 2025