Assertion without using clock

SystemVerilog
1

How to write a assertion for the 2 signals when signal1 is low then signal2 should be stable at 0 or 1 without using any clock.

I tried with this

 property p1;
     @(signal2) (signal1 != 0);
 endproperty

Thanks.

2 
//When signal1 goes low then no toggle in signal2
assert property(@(negedge signal1) 1 |-> 
  @(signal2) 0) ;

For other requirements,
Use automatic tasks. See my paper on modeling SVA
Understanding the SVA Engine Using the Fork-Join Model

Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.

3

Requirements: 1) if fall of sig1 then sig2 stable forever
2) // if fall of sig1 then sig2 stable until the next negedge of sig1
Two options. Other SV coding styles are possible. I like the task approach

module m;
  bit sig1, sig2;

  task automatic t_s1s2_stable();
    bit v;
    v=sig2;
    @(sig2) assert(sig2==v);
  endtask //automatic
  // if fall of sig1 then sig2 stable forever
  initial @(negedge sig1) t_s1s2_stable();

  task automatic t_s1s2_stable_till_s1();
    bit v;
    v=sig2;
    fork
      @(sig2) assert(sig2==v);
      @(sig1) assert(sig2==v);
     join_any
   endtask //automatic
 // if fall of sig1 then sig2 stable until the next negedge of sig1
   always @(negedge sig1) t_s1s2_stable_till_s1();
endmodule
4

hello ben,
in the above mentioned task t_s1s2_stable,if the value of sig2 changes then only we are checking the value which was before and after are same, how could this be possible, if there is a change how come it will same as before?
could you please give any insights into this?