Does a wait statement in a test main phase block the main phase execution of other testbench component's phases?

UVM
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1

Suppose I have the following code:

class abc_test extends base_test;
   `uvm_component_utils(abc_test)
   
    function new(string name, uvm_component parent);
      super.new(name);
    endfunction

  // configure_phase defined here
  
  task main_phase(uvm_phase);

    // wait for a DUT cnt to hit 100
    `uvm_info("MSG", $sformatf("Inside test main_phase: waiting for DUT counter to hit 100"), UVM_MEDIUM)
    
    wait(TB.DUT.modA.cnt == 'd100);

   `uvm_info("MSG", $sformatf("Inside test main_phase: DUT counter hit 100"), UVM_MEDIUM)

endtask

endclass

My questions are:

  1. Will the blocking wait statement in the test’s main phase also block execution of the driver’s main phase, or the sequencer’s main phase, or the env’s main phase etc.?

  2. When the test has a wait statement for a condition, is it just the test that waits for the condition?

  3. And is it true vice versa? Will a wait statement in the driver main phase block the execution of a monitor’s/test’s main phase?

2

The main_phase, or any task based phase of all uvm_components are forked as concurrent processes. A blocking statement in the main_phase task of a component only blocks that task.

At least one component must raise an objection to the phase ending for some period of time, otherwise , the phase will be terminated by killing all the tasks.

See End of Test | UVM Cookbook

3

Hi Dave, thank you for your reply.

If my test’s main_phase does not raise or drop any objection, but just has a wait statement as shown in the code above, and if all other components drop their objections in the main_phase, the test’s main_phase is killed and thus the wait statement is also killed.

Can you please let me know if my understanding is right?

4

Rather than telling you, I think you should make an example that will reinforce your understanding.

5

That’s true. Thank you Dave!