Suppose I have the following code:
class abc_test extends base_test;
`uvm_component_utils(abc_test)
function new(string name, uvm_component parent);
super.new(name);
endfunction
// configure_phase defined here
task main_phase(uvm_phase);
// wait for a DUT cnt to hit 100
`uvm_info("MSG", $sformatf("Inside test main_phase: waiting for DUT counter to hit 100"), UVM_MEDIUM)
wait(TB.DUT.modA.cnt == 'd100);
`uvm_info("MSG", $sformatf("Inside test main_phase: DUT counter hit 100"), UVM_MEDIUM)
endtask
endclass
My questions are:
-
Will the blocking wait statement in the test’s main phase also block execution of the driver’s main phase, or the sequencer’s main phase, or the env’s main phase etc.?
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When the test has a wait statement for a condition, is it just the test that waits for the condition?
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And is it true vice versa? Will a wait statement in the driver main phase block the execution of a monitor’s/test’s main phase?