Assertion to check weather a clock toggles or not

SystemVerilog
1

Can some one help me modify below code to check weather a clock toggles or not .
I tried writing down below two logics but it dose not seems to work

property serdes_tx_clk_toggle_check;
  @(posedge clk) disable iff (!rst_n)
  (serdes_tx_clk) |=> ~(serdes_tx_clk);  
  // ##1 (serdes_clk) |=> !(serdes_clk)
endproperty
  assert_serdes_tx_clk_toggle_check:assert property (serdes_tx_clk_toggle_check)
    else
     `ASSERT_ERROR("serdes_tx_clk Failed" ,$sformatf("serdes_tx_clk is not stoggling"))
2 
//logic to count clk posedge
always @(posedge clk)
cnt++;

property toggle_check;
@(posedge serdes_tx_clk) disable iff(!rst_n)
$rose(clk)|=> cnt==($past(cnt)+1);
endproperty
3

@red_pegasus_02 and @Abhinash_Prasad_Dash Please format your code making your code easier for others to read. I have done that for you both.

@red_pegasus_02 It would help to show a minimal, complete reproducible example

1 Like
4

what if there are multiple clocks for which I needed to write the check! then in that case according to your approach I need to write separate “cnt” variables for all the clocks in order to use it inside the individual property of all the clocks

5

@red_pegasus_02
What is relation between serdes_tx_clk & clk in terms of Clock period ?
Can Tclk & Tserdes_tx_clk be same as well or is one always greater than the other ?

6

I have binded my assertion file with a global clock and reset and I have written check for toggle for over 20 individual clocks so “serdes_tx_clk” is one of the clocks and “clk” is the global clock.

and frequency of the global clock(640 Mhz) and clocks present in the block are different.

7

A few things I observe ::
(1) You have modified ( swapped ‘clk’ & ‘serdes_tx_clk’ ) your original code at the top.
(2) You didn’t clarify the clock period of ‘serdes_tx_clk’ and the other 19 clocks

I understand that there are 20 individual clocks but isn’t their clock period known ?

As you have used global clock i.e “clk” as clocking event in your latest code,
I assume that “clk” would always be running / toggling.

8

the clock period of “serdes_tx_clk” is 640 Mhz and likewise the time period of other clocks are known . and are different form each other .

and “clk” which is the global clock is always toggling.