When designing a UVM testbench, I often face the challenge that two interfaces need to be aligned to each other and it would be nice if you could show a best practice on how this can be done.
Let me give you an example for that. Let’s assume we have a design with two inputs and one output as illustrated in the attached figure. The input data of interface A and B see a different number of pipeline stages, i.e. N and M, until they are combined in some combinatorial logic and forwarded to the output interface.
For the verification of such a design, I would create three instances of the same interface (two for the inputs and one for the output). The interface instances of input A and B would then send the monitored transactions to the reference model where a reference output transaction can be created. However, somewhere in my testbench I need to model the pipelining delay to ensure that I combine the correct input transactions with each other. How can this be done?
Possible solutions I see are:
delay the input transactions in their respective monitors according to the pipelining delay
monitor the current timestamp of the input transactions such that the reference model can align the input transactions
As neither solution seems elegant to me, I am looking forward to some guidance from your side.
If you really need 3 interfaces is unclear to me. An interface does not differentiate between inputs and outputs and you need only another interface if the pinlevel signals represent a different protocol or if they are independ interfaces. You should give some more explanations about this.
I changed the description of my question to clarify that I use three instances of the same interface. In case you need more details: The interface is simply enable driven, i.e. it contains of a data vector and a respective enable signal.
Looks like you have transaction-based ref model. Right? And the combinatorial logic at the output does not merge results from inputA with inputB? You could add an ID to your input transaction indicating comes from A or from B. Your ref model should be able to handle this.
Not exactly. My reference model is transaction based and contains two FIFOs (uvm_tlm_analysis_fifo). One for the transactions from port A and one for transactions from port B. However, the transactions that ultimately will be combined in the combinatorial logical will arrive at different points in time since the data through interface A needs to pass N pipeline stages and the data through interface B needs to pass M pipeline stages. If N is unequal to M, some mechanism is required to align the transactions.
So which approach would you recommend to verify the mentioned circuit?
Does it make sense to say that the pipeline stage offset between the inputs is somewhat part of the module’s protocol, such that the alignment could be handled in a shared interface for input A and B?
