Write a constraint to generate the pattern 1234554321

SystemVerilog
,
1

Write a constraint to generate the pattern 1234554321 Can you help me for this ?

2
3 
module check;
  class pattern;
    rand bit [31:0] arr[];
    
    constraint arr_size {arr.size inside {[10:20]}; (arr.size) % 2 == 0;}
    constraint pattern_c {foreach(arr[i]) {
      if(i == 0)  arr[i] == 1;
      else if(i < arr.size/2)  arr[i] == arr[i-1] + 1;
      else if(i == ((arr.size/2)))  arr[i] == arr[i-1];
      else if(i > arr.size/2)  arr[i] == arr[i-1] - 1;
   										  }}
    
  endclass
      
  initial begin
    pattern p = new;
    void'(p.randomize());
    $display("arr : %p",p.arr);
  end
endmodule

Output : 
arr : '{'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8, 'h9, 'h9, 'h8, 'h7, 'h6, 'h5, 'h4, 'h3, 'h2, 'h1}
1 Like
4 
class abc;
  
  rand bit[2:0] arr[];
  constraint a_constr{
    arr.size() == 10;
    foreach(arr[i]) {
      arr[0] == 1;
      if(i>0 && i<5) arr[i] == arr[i-1]+1'b1;
      if (i>5) arr[i] == arr[i-1]-1'b1;
    
    }
  }
    function void post_randomize();
    // foreach(arr[i,j])
    $display("arr == %0p", arr);
    endfunction
  
  
endclass: abc
    
    
    module tb;
      abc abc_inst;
      
      initial begin 
        abc_inst = new();
        abc_inst.randomize();
      end
      
      
    endmodule