Verification Academy

Topic	Replies	Views	Activity
Config_db - parameters for set/get method UVM UVM , config_db	28	12008	February 19, 2020
A constraint to generate odd_even_odd....... etc sequence SystemVerilog SystemVerilog , constraint , randomization	9	20361	June 9, 2017
Coverpoint for an array or queue Coverage Coverage	9	20181	May 31, 2021
Can we use system verilog properties/assertions inside a class? SystemVerilog SystemVerilog , system-verilog-assertion-SVA	13	16945	October 22, 2019
Package export does not work like I expect SystemVerilog SystemVerilog	14	15513	April 8, 2022
Timescale and Timeunit SystemVerilog SystemVerilog	11	17164	September 19, 2019
What is the best way to get a randomized real value? SystemVerilog SystemVerilog	9	18542	October 14, 2022
What is meant by a static class? SystemVerilog SystemVerilog	14	14938	September 4, 2024
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	23	11691	June 1, 2025
Counting number of events on clock a, while clock o is forbidden SystemVerilog SystemVerilog , assertion , first_match	24	11257	May 16, 2015
How to change random seed using command line parameter SystemVerilog SystemVerilog	9	17790	September 25, 2015
Sending data from monitor to sequence UVM UVM	36	9184	March 16, 2025
SystemVerilog Checker SystemVerilog SystemVerilog , system-verilog-checker	9	17526	July 20, 2020
[SVA] signal rises and stays stable check -> how to write an assertion? SystemVerilog SystemVerilog	20	11888	May 24, 2019
Constraint for one hot encoded vectors in SV SystemVerilog SystemVerilog	18	12315	August 2, 2023
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	8561	July 1, 2019
How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation? SystemVerilog SystemVerilog , never-rise , never-high	21	10784	March 25, 2017
Problem in unique of Constraint Randomization SystemVerilog SystemVerilog , constraint , unique	13	13313	April 29, 2016
Best way to introduce delay between sequences UVM UVM , sequence-delays	19	11101	May 24, 2019
Can the monitor communicate with the sequence directly? UVM UVM , driver , TLM-ports , Generating-sequences	17	11672	December 7, 2021
Working with multi-dimensional associative arrays SystemVerilog SystemVerilog , multi , dimensional , associative	11	14260	May 6, 2014
Assertion for ACK and REQ SystemVerilog SystemVerilog	12	13650	September 17, 2024
SV Assertions for Arbiter priority SystemVerilog SystemVerilog , assertion , Arbiter-priority	12	13533	April 25, 2020
Clock Frequency Checker SystemVerilog SystemVerilog , clock-frequency	12	13355	February 24, 2021
2D array constraint randomization SystemVerilog SystemVerilog , 2D-array-SystemVerilog-randomization	18	6176	November 24, 2024
Printing associative array SystemVerilog SystemVerilog , associative-array	9	14852	February 21, 2023
Prime numbers constraint SystemVerilog SystemVerilog	16	11339	October 7, 2024
UVM UVM UVM	71	5481	August 3, 2018
How to Sample data during Functional Coverage? Coverage Coverage , function-coverage , ignore-sampled-coverage-conditionaly-later	9	14562	October 10, 2017
Can i convert UVM_ERRORs to UVM_INFO or UVM_WARNING based on id? UVM UVM , convert , uvm_error , uvm_info , uvm_warning	9	14497	December 13, 2013
Use of regular expression for string comparison UVM UVM , regular-expressions	9	14386	May 19, 2021
Necessity of writing 'include "uvm_macros.svh" UVM UVM , uvm_macrossvh	12	12199	March 1, 2024
How to write assertions for a Clock divider SystemVerilog SystemVerilog	15	6121	April 24, 2025
Why we should use non-blocking assignments in driver and blocking assignments in monitor? UVM UVM	15	10799	December 8, 2024
Near "uvm_sequence_item": syntax error, unexpected IDENTIFIER UVM UVM	25	8208	August 2, 2017
How to delete duplicate elements from associative array and Queue in System Verilog SystemVerilog SystemVerilog , associative-array , accessing-the-associative-array-elements	15	10458	August 23, 2019
Override parameters in SV package SystemVerilog SystemVerilog	10	12578	September 25, 2024
Not registered with the factory UVM UVM	10	12479	January 15, 2024
Magic square on system verilog SystemVerilog SystemVerilog	18	5335	January 18, 2024
SVA evaluation SystemVerilog SystemVerilog	12	6391	March 25, 2022
“static task” vs. “task static” SystemVerilog SystemVerilog , static-task-method	14	10511	April 2, 2016
Burst Transfer SystemVerilog SystemVerilog , BURST-Transfer-AHB	9	12741	September 5, 2018
Error-[SE] Syntax error UVM UVM , syntax-error	13	10362	November 12, 2021
Can I trigger an event in one agent and after triggered, do something inside another agent? UVM UVM , uvm_event , multiple-agent , uvm_event_pool , trigger , event-trigger	14	9899	December 27, 2017
Dumping vcd files in a UVM test UVM SystemVerilog , UVM , VCD , vcd_files , dumpfile	12	10506	March 4, 2015
Random associative array SystemVerilog SystemVerilog	17	8927	October 12, 2022
Stoping a sequencer and starting it again in UVM UVM UVM , sequence , sequncer	13	9667	June 16, 2016
Exclude data from $urandom_range SystemVerilog SystemVerilog , randomization , urandom_range	9	11376	June 21, 2019
Specifying "ignore_bins = <everything else>" in coverpoint bins Coverage Coverage	9	11302	January 30, 2020
Fork-join_none with delay SystemVerilog SystemVerilog , for-loop-fork-join_none	31	6230	October 8, 2024