Verification Academy

Topic	Replies	Views	Activity
A constraint to generate odd_even_odd....... etc sequence SystemVerilog SystemVerilog , constraint , randomization	9	20268	June 9, 2017
How do I define an associative array of queues? SystemVerilog SystemVerilog , associative-array , Queues-in-system-verilog , systemverilog-Arrays	15	15916	August 19, 2022
Config_db - parameters for set/get method UVM UVM , config_db	28	11753	February 19, 2020
Coverpoint for an array or queue Coverage Coverage	9	19936	May 31, 2021
Can we use system verilog properties/assertions inside a class? SystemVerilog SystemVerilog , system-verilog-assertion-SVA	13	16725	October 22, 2019
Package export does not work like I expect SystemVerilog SystemVerilog	14	15241	April 8, 2022
Timescale and Timeunit SystemVerilog SystemVerilog	11	16907	September 19, 2019
What is the best way to get a randomized real value? SystemVerilog SystemVerilog	9	18273	October 14, 2022
What is meant by a static class? SystemVerilog SystemVerilog	14	14734	September 4, 2024
Counting number of events on clock a, while clock o is forbidden SystemVerilog SystemVerilog , assertion , first_match	24	11149	May 16, 2015
How to change random seed using command line parameter SystemVerilog SystemVerilog	9	17593	September 25, 2015
SystemVerilog Checker SystemVerilog SystemVerilog , system-verilog-checker	9	17265	July 20, 2020
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	22	11334	April 15, 2023
[SVA] signal rises and stays stable check -> how to write an assertion? SystemVerilog SystemVerilog	20	11687	May 24, 2019
Constraint for one hot encoded vectors in SV SystemVerilog SystemVerilog	18	12053	August 2, 2023
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	8357	July 1, 2019
How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation? SystemVerilog SystemVerilog , never-rise , never-high	21	10651	March 25, 2017
Problem in unique of Constraint Randomization SystemVerilog SystemVerilog , constraint , unique	13	13217	April 29, 2016
Can the monitor communicate with the sequence directly? UVM UVM , driver , TLM-ports , Generating-sequences	17	11566	December 7, 2021
Working with multi-dimensional associative arrays SystemVerilog SystemVerilog , multi , dimensional , associative	11	14026	May 6, 2014
Best way to introduce delay between sequences UVM UVM , sequence-delays	19	10860	May 24, 2019
SV Assertions for Arbiter priority SystemVerilog SystemVerilog , assertion , Arbiter-priority	12	13417	April 25, 2020
Assertion for ACK and REQ SystemVerilog SystemVerilog	12	13412	September 17, 2024
Clock Frequency Checker SystemVerilog SystemVerilog , clock-frequency	12	13117	February 24, 2021
UVM UVM UVM	71	5461	August 3, 2018
Printing associative array SystemVerilog SystemVerilog , associative-array	9	14534	February 21, 2023
Can i convert UVM_ERRORs to UVM_INFO or UVM_WARNING based on id? UVM UVM , convert , uvm_error , uvm_info , uvm_warning	9	14402	December 13, 2013
How to Sample data during Functional Coverage? Coverage Coverage , function-coverage , ignore-sampled-coverage-conditionaly-later	9	14387	October 10, 2017
Prime numbers constraint SystemVerilog SystemVerilog	16	10908	October 7, 2024
2D array constraint randomization SystemVerilog SystemVerilog , 2D-array-SystemVerilog-randomization	18	5784	November 24, 2024
Use of regular expression for string comparison UVM UVM , regular-expressions	9	14060	May 19, 2021
Necessity of writing 'include "uvm_macros.svh" UVM UVM , uvm_macrossvh	12	11906	March 1, 2024
Why we should use non-blocking assignments in driver and blocking assignments in monitor? UVM UVM	15	10472	December 8, 2024
Near "uvm_sequence_item": syntax error, unexpected IDENTIFIER UVM UVM	25	8095	August 2, 2017
How to delete duplicate elements from associative array and Queue in System Verilog SystemVerilog SystemVerilog , associative-array , accessing-the-associative-array-elements	15	10319	August 23, 2019
Override parameters in SV package SystemVerilog SystemVerilog	10	12297	September 25, 2024
Not registered with the factory UVM UVM	10	12207	January 15, 2024
“static task” vs. “task static” SystemVerilog SystemVerilog , static-task-method	14	10398	April 2, 2016
Burst Transfer SystemVerilog SystemVerilog , BURST-Transfer-AHB	9	12667	September 5, 2018
SVA evaluation SystemVerilog SystemVerilog	12	6232	March 25, 2022
Magic square on system verilog SystemVerilog SystemVerilog	18	5005	January 18, 2024
Can I trigger an event in one agent and after triggered, do something inside another agent? UVM UVM , uvm_event , multiple-agent , uvm_event_pool , trigger , event-trigger	14	9829	December 27, 2017
Dumping vcd files in a UVM test UVM SystemVerilog , UVM , VCD , vcd_files , dumpfile	12	10391	March 4, 2015
Random associative array SystemVerilog SystemVerilog	17	8756	October 12, 2022
Exclude data from $urandom_range SystemVerilog SystemVerilog , randomization , urandom_range	9	11234	June 21, 2019
Stoping a sequencer and starting it again in UVM UVM UVM , sequence , sequncer	13	9474	June 16, 2016
Specifying "ignore_bins = <everything else>" in coverpoint bins Coverage Coverage	9	11137	January 30, 2020
Clock generation through UVC UVM UVM , uvc , clock	15	8649	March 9, 2022
Fork-join_none with delay SystemVerilog SystemVerilog , for-loop-fork-join_none	31	6036	October 8, 2024
Error-[TMAFTC] Too many arguments to function/task call UVM UVM , Compile-UVM-12-in-Windos-64-bit	12	9335	July 18, 2018