Verification Academy

Topic	Replies	Views	Activity
Coverpoint for an array or queue Coverage Coverage	9	19551	May 31, 2021
Config_db - parameters for set/get method UVM UVM , config_db	28	11377	February 19, 2020
Can we use system verilog properties/assertions inside a class? SystemVerilog SystemVerilog , system-verilog-assertion-SVA	13	16344	October 22, 2019
Package export does not work like I expect SystemVerilog SystemVerilog	14	14860	April 8, 2022
Timescale and Timeunit SystemVerilog SystemVerilog	11	16535	September 19, 2019
What is the best way to get a randomized real value? SystemVerilog SystemVerilog	9	17861	October 14, 2022
Regarding Race Condition SystemVerilog SystemVerilog	10	17000	March 14, 2023
Counting number of events on clock a, while clock o is forbidden SystemVerilog SystemVerilog , assertion , first_match	24	10936	May 16, 2015
How to change random seed using command line parameter SystemVerilog SystemVerilog	9	17272	September 25, 2015
SystemVerilog Checker SystemVerilog SystemVerilog , system-verilog-checker	9	16927	July 20, 2020
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	22	10869	April 15, 2023
[SVA] signal rises and stays stable check -> how to write an assertion? SystemVerilog SystemVerilog	20	11324	May 24, 2019
Constraint for one hot encoded vectors in SV SystemVerilog SystemVerilog	18	11688	August 2, 2023
What is meant by a static class? SystemVerilog SystemVerilog	11	14389	July 15, 2019
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	8022	July 1, 2019
Problem in unique of Constraint Randomization SystemVerilog SystemVerilog , constraint , unique	13	13001	April 29, 2016
How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation? SystemVerilog SystemVerilog , never-rise , never-high	21	10369	March 25, 2017
Can the monitor communicate with the sequence directly? UVM UVM , driver , TLM-ports , Generating-sequences	17	11331	December 7, 2021
SV Assertions for Arbiter priority SystemVerilog SystemVerilog , assertion , Arbiter-priority	12	13181	April 25, 2020
Working with multi-dimensional associative arrays SystemVerilog SystemVerilog , multi , dimensional , associative	11	13669	May 6, 2014
Best way to introduce delay between sequences UVM UVM , sequence-delays	19	10463	May 24, 2019
Clock Frequency Checker SystemVerilog SystemVerilog , clock-frequency	12	12769	February 24, 2021
Can i convert UVM_ERRORs to UVM_INFO or UVM_WARNING based on id? UVM UVM , convert , uvm_error , uvm_info , uvm_warning	9	14189	December 13, 2013
UVM UVM UVM	71	5264	August 3, 2018
Printing associative array SystemVerilog SystemVerilog , associative-array	9	14110	February 21, 2023
How to Sample data during Functional Coverage? Coverage Coverage , function-coverage , ignore-sampled-coverage-conditionaly-later	9	14067	October 10, 2017
Use of regular expression for string comparison UVM UVM , regular-expressions	9	13638	May 19, 2021
Necessity of writing 'include "uvm_macros.svh" UVM UVM , uvm_macrossvh	12	11527	March 1, 2024
How to delete duplicate elements from associative array and Queue in System Verilog SystemVerilog SystemVerilog , associative-array , accessing-the-associative-array-elements	15	10024	August 23, 2019
Near "uvm_sequence_item": syntax error, unexpected IDENTIFIER UVM UVM	25	7849	August 2, 2017
Prime numbers constraint SystemVerilog SystemVerilog	14	10304	June 26, 2024
Burst Transfer SystemVerilog SystemVerilog , BURST-Transfer-AHB	9	12474	September 5, 2018
“static task” vs. “task static” SystemVerilog SystemVerilog , static-task-method	14	10148	April 2, 2016
Not registered with the factory UVM UVM	10	11825	January 15, 2024
SVA evaluation SystemVerilog SystemVerilog	12	5983	March 25, 2022
Override parameters in SV package SystemVerilog SystemVerilog	9	11872	August 10, 2023
Why we should use non-blocking assignments in driver and blocking assignments in monitor? UVM UVM	13	10011	July 19, 2023
Can I trigger an event in one agent and after triggered, do something inside another agent? UVM UVM , uvm_event , multiple-agent , uvm_event_pool , trigger , event-trigger	14	9620	December 27, 2017
Dumping vcd files in a UVM test UVM SystemVerilog , UVM , VCD , vcd_files , dumpfile	12	10136	March 4, 2015
Random associative array SystemVerilog SystemVerilog	17	8461	October 12, 2022
Magic square on system verilog SystemVerilog SystemVerilog	18	4604	January 18, 2024
Exclude data from $urandom_range SystemVerilog SystemVerilog , randomization , urandom_range	9	10961	June 21, 2019
Specifying "ignore_bins = <everything else>" in coverpoint bins Coverage Coverage	9	10868	January 30, 2020
Stoping a sequencer and starting it again in UVM UVM UVM , sequence , sequncer	13	9160	June 16, 2016
Clock generation through UVC UVM UVM , uvc , clock	15	8387	March 9, 2022
Error-[TMAFTC] Too many arguments to function/task call UVM UVM , Compile-UVM-12-in-Windos-64-bit	12	9017	July 18, 2018
VHDL record to Systemverilog struct SystemVerilog SystemVerilog , vhdl-record-struct-mapping	11	9256	July 1, 2014
Assertion stable after two or more rising edge UVM UVM , assertion , fell , stable	11	9244	March 28, 2017
Can we sample coverpoints which are design parameters? Coverage Coverage	14	8197	February 8, 2019
RAL Backdoor access UVM UVM	14	8087	August 23, 2016