Hi,
Is there any method to write a one hot coded series of vectors as a constraint. For eg I require twenty five 25 bit vectors, like
constraint {bin inside {
25’b0000000000000000000000001,
25’b0000000000000000000000010,
25’b0000000000000000000000100,
25’b0000000000000000000001000,
…}
}
It would be tedious to do so for a 25 bit vector. Is there any other method to do so in SV?
In reply to Gokul S:
You can use the $countones system function.
std::randomize (some_var) with {$countones(some_var) == 1;};
In reply to sbellock:
Thanks, but all generated vectors will be random, ryt? I need to ensure all the 25 bit one hot encoded vectors are inside my range. How is that possible?
In reply to Gokul S:
You were not clear on your requirements. If you need to generate 25 25-bit one-hot numbers and don’t care about repetition the constraint that Steve gave you works if you call randomize 25 times. If you do not want repetition, use the randc qualifier as shown below.
module top;
class A;
randc [24:0] vector;
constraint one hot { $countones(vector) == 1; }
endclass
A h;
initial begin
h = new;
repeat (25) begin
assert (h.randomize());
$displayb(h.vector);
end
end
endmodule
In reply to dave_59:
In reply to Gokul S:
You were not clear on your requirements. If you need to generate 25 25-bit one-hot numbers and don’t care about repetition the constraint that Steve gave you works if you call randomize 25 times. If you do not want repetition, use the randc qualifier as shown below.
module top;
class A;
randc [24:0] vector;
constraint one hot { $countones(vector) == 1; }
endclass
A h;
initial begin
h = new;
repeat (25) begin
assert (h.randomize());
$displayb(h.vector);
end
end
endmodule
I thought randc can take only a max of 16 bits for a possible 65536 values.
In reply to raja7052:
In this case, there are only 25 possible values. The limits for randc is simulator specific.
Hi Dave,
I ran the program and i am getting compile Error. Can you help?
module top;
class A;
randc bit [24:0] vector;
constraint one_hot { $countones(vector) == 1; }
endclass
A h;
initial begin
h = new;
repeat (25) begin
assert (h.randomize());
$displayb(h.vector);
end
end
endmodule
rror-[IVCB-NORANDC] Illegal use of randc variable
design.sv, 5
top, “this.vector”
The expression contains the variable vector of type randc and cannot be used
in solve-before, distribution, unique and function calls.
Change the type of the randc variable or remove it from the expression.
In reply to dave_59:
Hi Dave ,
LRM says that "randc Variables are always solved first ", i.e even before random variables as input arguments to Functions Called in Constraints
[1] So once a value of randc is chosen it won’t be chosen again ( if called as Input Argument ) ?
Regards,
AGIS
In reply to Etrx91:
Built-in SV functions are not treated the same as user defined functions. They can be inlined into the constraint expression.
In reply to dave_59:
Hi Dave ,
So what would be the Order in which they are solved ?
" randc Variables VS Built-in SV Functions VS User Defines Functions "
randc Varaiables I understand would be solved First , what about the solving order between the other 2 Functions ? .
Regards,
AGIS
In reply to Etrx91:
Once a function is in-lined, there is no longer an ordering issue. The constraint becomes
(vector[0] + vector[1] + vector[2] + ...) == 1
Hi Dave,
I tried to this using a dynamic array but, it is not working for me. IN EDA playground it is timing out. Not sure if there is any issue in my constraint. I should try this probably in my work place environment and, see as well.
This is getting timed out after a min or 2. Is this some stack mem limitation of EDA Tools that is using Synopsys VCS 2014.
module top;
class A;
rand bit [24:0] vector[];
constraint one_hot {
vector.size() == 25;
foreach(vector[i])
$countones(vector[i]) == 1;
}
constraint c_uniq {
unique {vector};
}
endclass
//A h;
module top ();
initial begin
A h = new;
//repeat (25) begin
assert (h.randomize());
$displayb(h.vector);
//end
end
endmodule
In reply to sriram.seshagiri:
This is an old tool issue. Try a different one.
BTW, A h = new() is not allowed because h has a implicit static lifetime. Please see this.
In reply to dave_59:
Hello Dave,
Using systemfunctions inside constraints is not supported yet by my simulator. Is there any other way of doing it??
In reply to Husni Mahdi:
The following constraint will generate the one-hot vector however it will not generated walking one pattern ;
module top ;
class onehot ;
rand bit [24:0] vector ;
constraint c_vector {
(vector & (vector-1)) == 0;
}
endclass
initial begin
onehot o ;
o = new ;
repeat(10)begin
o.randomize();
$display("%b",o.vector);
end
end
endmodule