Constraint for one hot encoded vectors in SV

SystemVerilog
6

In reply to dave_59:

In reply to Gokul S:
You were not clear on your requirements. If you need to generate 25 25-bit one-hot numbers and don’t care about repetition the constraint that Steve gave you works if you call randomize 25 times. If you do not want repetition, use the randc qualifier as shown below.

module top;
class A;
randc [24:0] vector;
constraint one hot { $countones(vector) == 1; }
endclass
A h;
initial begin
h = new;
repeat (25) begin
assert (h.randomize());
$displayb(h.vector);
end
end
endmodule

I thought randc can take only a max of 16 bits for a possible 65536 values.