Not registered with the factory

UVM
1

Hello,

Can someone refer me to link explaining the following error:

Cannot create a component of type 'test' because it is not registered with the factory.

Regards
Sunil Sharma

2

In reply to sunils:

Hi Sunil,
Did you use the macro `uvm_compopenet_utils() in your testcasae?

Using this macro registers the class with the factory.

Thanks,
Suyog

3

In reply to sree205:

Hello Suyog,

Thanks, I have used the `uvm_component_utils, but still it gives the same error.

Thanks.

4

In reply to sunils:

Can you provide some additional context regarding where you are seeing this message? Is it related to a call to create() or run_test()?

Since you indicated you are trying to create a component named ‘test’, I’m going to guess it is related to the run_test() call. If this is the case, did you make sure that you imported your package containing your test? If the package isn’t imported, it won’t be able to create a component of that type.

5

In reply to cgales:

Hello Cgales,

I am getting the following error giving in detail:

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'mem_ss_test' because it is not registered with the factory.
# UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=mem_ss_test not found.
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :    2
# UVM_WARNING :    1
# UVM_ERROR :    0
# UVM_FATAL :    1

Plus:

  1. I am compiling(not importing) the package containing the mem_ss_test. I am not sure where to import the package. This package contains all the environmental files.

  2. I am calling the test from +UVM_TESTNAME=mem_ss_test cmd line.

Please help and suggest.

Thanks and Regards
Sunil S.

6

In reply to sunils:

Hello Cgales,

It is working after importing the package in the tb top module. Thanks a lot. Thank you…

Regards
Sunil

7

In reply to sunils:

Hello Sunil,

I have used `uvm_compopenet_utils() but still I am facing the same issue.
Could you please let me know where and which package exactly u imported??

Regards,
Dilip Kumar Erappa

8

In reply to DK2894erappa:

The package is the one containing the class declaration you want to use with +UVM_TESTNAME=name. That package has to be imported by some module/inteface used in your testbench, usually the module containing the call to run_test();. It can also be indirectly imported by another package, but that package would also need to be imported by some module/interface used in the testbench.

9

In reply to sunils:

Hello sunils,

i am also facing same error but my question is diff. in package.sv file we have all component till test.sv and we `include"package.sv" in our top file so as per my understanding if we include any file in an other file we give access to top.sv that “physically place the package.sv code of a file while compiling” by using dave_59 blog. so test.sv file which is present in package will be work on top so why import ?

what diff. import created
or else we directly include testfile in top without import.

10

A package is a precompiled set of definitions such as parameters, typedefs, classes, etc. You then import it into a module or another package, making the definitions available. Importing a package is faster than including a bunch of source files.

  1. Put every class in a separate file
  2. In a package, include all your classes, such as sequence items, sequences, components, and many tests
  3. Compile the package
  4. Import the package in your test module, don’t include it
  5. Compile the test module
  6. Run the sim with +UVM_TESTNAME to pick the one test to run
1 Like
11

Hi Chrisspear,

Thanks for the explanation.