Can we use system verilog properties/assertions inside a class?

SystemVerilog
,
1

Hi,
I am willing to check the properties of some of the variables inside a class.But i am getting an error like this

ncvlog: *E,ADBLCK (class_rand.sv,35|11): SystemVerilog assertion, property or sequence declarations are illegal as a function declaration item.
property p_m_clk_lo;
|
ncvlog: *E,ADBLCK (class_rand.sv,41|11): SystemVerilog assertion, property or sequence declarations are illegal as a function declaration item.
ap_hi: assert property(p_m_clk_hi)

Question : Can we use properties inside a class? If it is valid can you please explain with an example.

Thanks,
Tarun

2

In reply to perumallatarun:
Concurrent assertions are not allowed in classes; this is because classes are dynamic, and there are issues in having concurrent assertions in classes. However, you can put the assertions in SystemVerilog interfaces. I address that topic in the following papers:
“Using SVA for scoreboarding and TB designs”

and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-9_issue-3/articles/stream/assertions-instead-of-fsms-logic-for-scoreboarding-and-verification_vh-v9-i3.pdf

and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Thank you Ben.

But I did not understand why we are unable to use concurrent assertions inside a class. Can you please mention the reasons for it.

4

In reply to perumallatarun:
I am on the SV-AC committee. Issues are with the dynamic nature of classes.

SV-AC recommends to create a cross-P1800 group to study the following proposal and to elaborate recommendations for the future work:

5068: concurrent assertions in classes
https://accellera.mantishub.io/view.php?id=5068

Ben@systemverilog

5

In reply to ben@SystemVerilog.us:

In reply to perumallatarun:
I am on the SV-AC committee. Issues are with the dynamic nature of classes.

Concurrent assertions require some synthesis-like analysis, and someone needs to come up with the synthesis semantics for class-based code for this to work.

6

In reply to dave_59:

Thank you Ben and Dave.

7

In reply to sarang.p:

5068: concurrent assertions in classes
That was a suggestion for consideration, but the SVA committee decided not to adopt it because of its complexities.
Ben systemverilog.us

8

In reply to ben@SystemVerilog.us:

In reply to sarang.p:
5068: concurrent assertions in classes
That was a suggestion for consideration, but the SVA committee decided not to adopt it because of its complexities.
Ben systemverilog.us

Take a look at my psper

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
9

In reply to ben@SystemVerilog.us:
Updated Link
https://accellera.mantishub.io/view.php?id=5068

10

In reply to perumallatarun:

Lots of high level synthesis stuff such as Mentor Catapult tool support class synthesis without any issues.
So I assume it is matter of time, after while SV will support concurrent assignment in the class.

11

In reply to haykp:

“So I assume it is matter of time, after while SV will support concurrent assignment in the class”
I wouldn’t hold my breath on having concurrent assertions in classes.
Because of the dynamic life of a class (newed, killed, copied or relinked} classes offer too many complexities to be addressed. Also, is typically time-limited, and the importance of SVA in classes is not something of high demand. My paper shows that the assertions can exist in interfaces and class vari3can be copied into the interfaces.

In general, making big changes in a spec is very difficult and requires lots of backup material and need and analysis to make that happening.
Ben systemverilog.us

12

In reply to dave_59:

Hi dave_59,

The example you provided in this link https://accellera.mantishub.io/file_download.php?file_id=5950&type=bug is not working in my tool.
I used cadence tool. It showing an error like SystemVerilog assertion, property or sequence declarations are illegal as a function declaration item
Can you give some information about this??

Thanks
T. Siva Prasad

13

In reply to Siva91221:
It’s not a tool issue. 1800’2017 does not allow concurrent assertions in classes.
You can emulate sva using tasks; works in classes too.
See my paper
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue

Ben systemverilog.us

14

In reply to Siva91221:

The example you posted is part of an unimplemented enhancement request to SystemVerilog.