Can we use system verilog properties/assertions inside a class?

SystemVerilog
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In reply to ben@SystemVerilog.us:

In reply to sarang.p:
5068: concurrent assertions in classes
That was a suggestion for consideration, but the SVA committee decided not to adopt it because of its complexities.
Ben systemverilog.us

Take a look at my psper

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue