In reply to dave_59:
Hi dave_59,
The example you provided in this link https://accellera.mantishub.io/file_download.php?file_id=5950&type=bug is not working in my tool.
I used cadence tool. It showing an error like SystemVerilog assertion, property or sequence declarations are illegal as a function declaration item
Can you give some information about this??
Thanks
T. Siva Prasad