Can we use system verilog properties/assertions inside a class?

In reply to haykp:

“So I assume it is matter of time, after while SV will support concurrent assignment in the class”
I wouldn’t hold my breath on having concurrent assertions in classes.
Because of the dynamic life of a class (newed, killed, copied or relinked} classes offer too many complexities to be addressed. Also, is typically time-limited, and the importance of SVA in classes is not something of high demand. My paper shows that the assertions can exist in interfaces and class vari3can be copied into the interfaces.

In general, making big changes in a spec is very difficult and requires lots of backup material and need and analysis to make that happening.
Ben systemverilog.us