In reply to perumallatarun:
Concurrent assertions are not allowed in classes; this is because classes are dynamic, and there are issues in having concurrent assertions in classes. However, you can put the assertions in SystemVerilog interfaces. I address that topic in the following papers:
“Using SVA for scoreboarding and TB designs”
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-9_issue-3/articles/stream/assertions-instead-of-fsms-logic-for-scoreboarding-and-verification_vh-v9-i3.pdf
and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115