Can we use system verilog properties/assertions inside a class?

SystemVerilog
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4

In reply to perumallatarun:
I am on the SV-AC committee. Issues are with the dynamic nature of classes.

SV-AC recommends to create a cross-P1800 group to study the following proposal and to elaborate recommendations for the future work:

5068: concurrent assertions in classes
https://accellera.mantishub.io/view.php?id=5068

Ben@systemverilog