Can we use system verilog properties/assertions inside a class?

In reply to Siva91221:
It’s not a tool issue. 1800’2017 does not allow concurrent assertions in classes.
You can emulate sva using tasks; works in classes too.
See my paper
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue

Ben systemverilog.us