Override parameters in SV package

SystemVerilog
1

I have this generic package file that has a parameter for a default ID. What is the proper way to override that parameter? Is it to declare another package with the same parameter and compile it first? or is there a keyword to use?

2

In reply to VerifEx:

There is no way to override a parameter in a package. You can declare a class in the package and override the class parameter when you reference the class.

Other things you can do:

You can create different versions of the same package and choose which version to compile.

You can use define a text macro on the command line that can be used by the package to set the parameter value.

3

In reply to dave_59:

Dave,

i have also ran into this problem recently. I have DUT with a fair amount of parameters/generics. I have created a shared package that links the changes in the generics to uvm test fields. Now i realise this won’t work.

Can you elaborate on that 2nd option? I haven’t had much need to play with text macros in SV so far.

Thanks!

4

In reply to Phill_Ferg:
my_package.sv:

package my_package;
parameter my_parameter = `MY_DEFINE;
endpackage

Om your compiler command line

compile my_package.sv +define+MY_DEFINE=4
2 Likes
5

In reply to Phill_Ferg:

You shouldn’t need -floatparamters since the parameter is comping from a compiled package, and you need to re-compile the package to change a parameter’s value. You’re getting into the territory of tool-specific behavior, and this forum is not tool specific support.

6

In reply to dave_59:

Agreed! I release i was close to the edge. Thanks for your help!

7

In reply to dave_59:

“You can declare a class in the package and override the class parameter when you reference the class”

could you please give an example for this?
i have a class in the package and the parameter is declared inside the class.
how to override that parameter?

8

In reply to Liiiiiz:

package my_package;
  class my_class #(int my_parameter);
    function int get_parameter;
       return my_parameter;
    endfunction
  endclass
endpackage

module top;
import my_package::*;
   my_class#(1) c1=new;
   my_class#(2) c2=new;
   initial begin
     $display(c1.get_parameter);
     $display(c2.get_parameter);
   end
endmodule
9

In reply to Liiiiiz:

As was stated earlier, SystemVerilog does not provide a mechanism to override parameters declared in the top-level of a package. You need to describe what you are trying to accomplish. See https://xyproblem.info/

10

In reply to dave_59:

Hi Dave, please find the problem (hopefully better explained)

I have a class cg_wrap which has parameters A1-A4 as defined below which are used in the covergroup cg_wrap_1. The task sample() for the covergroup cg_wrap_1 is called in the coverage_collector class.

My intention is to override the parameters A1 and A2 such that when the task sample() is called, the coverpoints should check the signal with parameter value A1=11, A2=12 and not A1=10 and A1=20.

package my_pkg;

import uvm_pkg::*;

`include "uvm_macros.svh"

class cg_wrap #(
  parameter A1 = 10,
  parameter A2 = 20,
   parameter A3 = 30,
   parameter A4 = 40
) extends uvm_sequence_item;

  `uvm_object_param_utils(cg_wrap))
 
  function new(string name="cg_wrap");
    super.new(name);       
      endfunction
 
  covergroup cg_wrap_1 with function sample();
    cp_xyz : coverpoint xyz {
            bins min = {0};
            bins min_p1 = {1};
            bins max_m1 = { A1 - 1};
            bins max = { A1 };
            }
         
    cp_abc : coverpoint abc {
            bins min = {0};
            bins min_p1 = {1};
            bins max_m1 = { A2 - 1};
            bins max = { A2 };
            }
     endgroup

      function new(string name="cg_wrap_1");
         super.new();
         cg_wrap_1 = new();          
         cg_wrap_1.set_inst_name($sformatf("%s", name)); 
      endfunction

      function void sample();
         cg_wrap_1.sample();
      endfunction

endclass


class coverage_collector extends uvm_subscriber#(uvm_sequence_item);

   `uvm_component_utils(coverage_collector)
  uvm_analysis_port #(uvm_sequence_item) to_receiver;
  cg_wrap pkt_cov;
 
   function new(string name, uvm_component parent);
      super.new(name,parent);
      to_receiver   = new ("to_receiver", this);  
      pkt_cov = cg_wrap::type_id::create("cg_wrap");
   endfunction : new
  
   task run_phase (uvm_phase phase);
      `uvm_info("UVC","run_phase: Executing.   coverage_collector run_phase<<<",UVM_LOW) 
    endtask : run_phase
  
  task sample_and_transmit();
         pkt_cov.sample();
         to_receiver.write(pkt_cov); 
      endtask

  function void write(uvm_sequence_item t);
   //placeholder 
  endfunction

endclass : coverage_collector

endpackage : my_pkg
11

Thanks for this reply in this thread.
To be clear, `MY_DEFINE macro can be used throughout the testbench code, including other packages, tests, sequences, and the testbench module?
Are there limitations to using this method?