In reply to Liiiiiz:
As was stated earlier, SystemVerilog does not provide a mechanism to override parameters declared in the top-level of a package. You need to describe what you are trying to accomplish. See https://xyproblem.info/
In reply to Liiiiiz:
As was stated earlier, SystemVerilog does not provide a mechanism to override parameters declared in the top-level of a package. You need to describe what you are trying to accomplish. See https://xyproblem.info/