Override parameters in SV package

SystemVerilog
8

In reply to Liiiiiz:

package my_package;
  class my_class #(int my_parameter);
    function int get_parameter;
       return my_parameter;
    endfunction
  endclass
endpackage

module top;
import my_package::*;
   my_class#(1) c1=new;
   my_class#(2) c2=new;
   initial begin
     $display(c1.get_parameter);
     $display(c2.get_parameter);
   end
endmodule