I have the following code in one of the files (pakmx_sequence.sv)
//----------------------------------------------------------------------
//Sequence
//----------------------------------------------------------------------
class pakmx_transaction extends uvm_sequence_item;
//packet’s data - rand
bit[1:0] target;
bit[5:0] lengths;
bit[7:0] data [37:0];
//checksum- not rand
bit[7:0] checksum;
//new
function new(string name = “”);
super.new(name);
endfunction: new
//function my_random
function void my_randomize()
target = $urandom_range(2,1);
lengths = $urandom_range(4,38);
foreach(data[index]) begin
data[index] = $urandom % 255;
end
endfunction: my_randomize()
endclass: pakmx_transaction
class pakmx_sequence extends uvm_sequence#(pakmx_transaction);
`uvm_object_utils(pakmx_sequence)
function new(string name = "");
super.new(name);
endfunction: new
task body();
pakmx_transaction pm_tx;
repeat(15) begin
pm_tx = pakmx_transaction::type_id::create(.name("pm_tx"), .contxt(get_full_name()));
start_item(pm_tx);
//assert(pm_tx.my_randomize());
finish_item(pm_tx);
end
endtask: body
I compile my project with the following script:
vmap work work
vlog +incdir+./uvm-1.2/src ./uvm-1.2/src/uvm_pkg.sv ./uvm-1.2/src/dpi/uvm_dpi.cc -ccflags -DQUESTA
vlog design_hdl/packet_mux.sv
vlog pakmx_if.sv
vlog pakmx_sequence.sv pakmx_agent.sv pakmx_env.sv pakmx_test.sv pakmx_driver.sv pakmx_pkg.sv pakmx_tb_top.sv
When I try to compile I get some errors. The first is:
** Error: (vlog-13069) pakmx_sequence.sv(4): near “uvm_sequence_item”: syntax error, unexpected IDENTIFIER.
In reply to saritr:
Typically you `include files into a package instead of putting the file on the command line. Which file defines the package that defines paknx_transaction?
Can you post the part of code from package where you are including pakmx_sequence.sv?
Also, along with uvm_pkg import, you should also have `include “uvm_macros.svh” as well.
In reply to saritr:
Can you post the part of code from package where you are including pakmx_sequence.sv?
Also, along with uvm_pkg import, you should also have `include “uvm_macros.svh” as well.
Please check for the errors in your pakmx_config.sv (like missing endclass or missing guards etc) because sometimes I faced an issue of such kind due to the errors in the previous compiled files(If you think every think is imported properly and put in a package).
In reply to saritr:
Hi,
Please check for the errors in your pakmx_config.sv (like missing endclass or missing guards etc) because sometimes I faced an issue of such kind due to the errors in the previous compiled files(If you think every think is imported properly and put in a package).
That’s what I have in the config file:
class pakmx_config extends uvm_object;
`uvm_object_utils(pakmx_config)
function new(string name = "");
super.new(name);
endfunction: new
I wrote in the compile script the following:
vmap work work
vlog +incdir+./uvm-1.2/src ./uvm-1.2/src/uvm_pkg.sv ./uvm-1.2/src/dpi/uvm_dpi.cc -ccflags -DQUESTA\ pakmx_config.sv pakmx_sequence.sv pakmx_agent.sv pakmx_env.sv pakmx_test.sv pakmx_driver.sv pakmx_pkg.sv pakmx_tb_top.sv
vlog -vs +incdir+./uvm-1.2/src/uvm_macros.svh
vlog design_hdl/packet_mux.sv
vlog pakmx_if.sv
In reply to saritr:
Can you go with other two approaches, which is not using vlog command multiple times.
In this case, when we compile all test files first, pakmx_tb_top.sv file also requires DUT and Interface as well, and that is being compiled with later vlog commands.
Or use this,
I did the following:
vmap work work
vlog ./design_hdl/packet_mux.sv pakmx_if.sv +incdir+./uvm-1.2/src ./uvm-1.2/src/uvm_pkg.sv ./uvm-1.2/src/dpi/uvm_dpi.cc -ccflags -DQUESTA pakmx_config.sv pakmx_sequence.sv pakmx_agent.sv pakmx_env.sv pakmx_test.sv pakmx_driver.sv pakmx_pkg.sv pakmx_tb_top.sv
It’s more or less confusing what you are doing. I gues you are looking for a general approach how to compile a UVM environment. To get such an approach you should pack together what belongs together, i.e. having packages for all agents, test, and the top_tb. These are the 3 main parts of your UVM environment.
Download from my webpage www.christoph-suehnel.de a running example and look in the sim-directory for a the compile-script compile.do. Follow the instructions there.
BTW +incdir+ has to point to a folder and not to a file.
Compiling class files has no point here. Only compile files which are modules(module, package, interface.) with vlog command. And include all class files in top module or package.
In reply to saritr:
Can you post the error message? Correction:
Compiling class files has no point here. Only compile files which are modules(module, package, interface.) with vlog command. And include all class files in top module or package.
C:\pk_mux>run_scr.bat
C:\pk_mux>vmap work work
Model Technology ModelSim PE vmap 10.4c Lib Mapping Utility 2015.07 Jul 20 2015
vmap work work
Modifying modelsim.ini
C:\pk_mux>vlog ./design_hdl/packet_mux.sv pakmx_if.sv +incdir+./uvm-1.2/src ./uv
m-1.2/src/uvm_pkg.sv ./uvm-1.2/src/dpi/uvm_dpi.cc -ccflags -DQUESTA pakmx_config
.sv pakmx_sequence.sv pakmx_agent.sv pakmx_env.sv pakmx_test.sv pakmx_driver.sv
pakmx_pkg.sv pakmx_tb_top.sv
Model Technology ModelSim PE vlog 10.4c Compiler 2015.07 Jul 20 2015
Start time: 09:31:36 on Aug 02,2016
vlog ./design_hdl/packet_mux.sv pakmx_if.sv “+incdir+./uvm-1.2/src” ./uvm-1.2/sr
c/uvm_pkg.sv ./uvm-1.2/src/dpi/uvm_dpi.cc -ccflags -DQUESTA pakmx_config.sv pakm
x_sequence.sv pakmx_agent.sv pakmx_env.sv pakmx_test.sv pakmx_driver.sv pakmx_pk
g.sv pakmx_tb_top.sv
– Compiling module packet_mux
– Compiling interface pakmx_if
– Compiling package uvm_pkg
** Warning: ./uvm-1.2/src/seq/uvm_sequencer_base.svh(1499): (vlog-2186) SystemVe
rilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: ./uvm-1.2/src/seq/uvm_sequencer_base.svh(1662): (vlog-2186) SystemVe
rilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: ./uvm-1.2/src/seq/uvm_sequence_base.svh(1333): (vlog-2186) SystemVer
ilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Error: (vlog-13069) pakmx_config.sv(2): near “uvm_object”: syntax error, unex
pected IDENTIFIER.
** Error: pakmx_config.sv(2): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “uvm_sequence_item”: syntax erro
r, unexpected IDENTIFIER.
** Error: pakmx_config.sv(5): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “uvm_agent”: syntax error, unexp
ected IDENTIFIER.
** Error: pakmx_config.sv(5): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “uvm_env”: syntax error, unexpec
ted IDENTIFIER.
** Error: pakmx_config.sv(5): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “uvm_test”: syntax error, unexpe
cted IDENTIFIER.
** Error: pakmx_config.sv(5): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “uvm_driver”: syntax error, unex
pected IDENTIFIER.
** Error: pakmx_config.sv(5): Error in class extension specification.
** Error: (vlog-13069) pakmx_config.sv(5): near “#”: syntax error, unexpected '#
', expecting class.
** Error: pakmx_tb_top.sv(5): Illegal use of ‘automatic’ for variable declaratio
n (rst).
** Error: pakmx_tb_top.sv(5): Illegal use of ‘automatic’ for variable declaratio
n (clk).
** Error: (vlog-13069) pakmx_driver.sv(5): near “(”: syntax error, unexpected '(
', expecting class.
– Compiling DPI/PLI C++ file ./uvm-1.2/src/dpi/uvm_dpi.cc
./uvm-1.2/src/dpi/uvm_hdl_questa.c: In function ‘int uvm_hdl_set_vlog_partsel(ch
ar*, t_vpi_vecval*, PLI_INT32)’:
./uvm-1.2/src/dpi/uvm_hdl_questa.c:111: warning: control reaches end of non-void
function
./uvm-1.2/src/dpi/uvm_hdl_questa.c: In function ‘int uvm_hdl_get_vlog_partsel(ch
ar*, t_vpi_vecval*, PLI_INT32)’:
./uvm-1.2/src/dpi/uvm_hdl_questa.c:172: warning: control reaches end of non-void
function
End time: 09:31:38 on Aug 02,2016, Elapsed time: 0:00:02
Errors: 16, Warnings: 3
In reply to mayurkubavat:
It’s more or less confusing what you are doing. I gues you are looking for a general approach how to compile a UVM environment. To get such an approach you should pack together what belongs together, i.e. having packages for all agents, test, and the top_tb. These are the 3 main parts of your UVM environment.
Download from my webpage www.christoph-suehnel.de a running example and look in the sim-directory for a the compile-script compile.do. Follow the instructions there.
BTW +incdir+ has to point to a folder and not to a file.
From where exactly I have to download the example?
Include all your testbench class files in a package, import this package in top module. And you need to compile this package with top module and interface.
Or 2) If you are compiling tb class files with vlog, you need to import uvm_pkg globally, outside module. e.g.