Near "uvm_sequence_item": syntax error, unexpected IDENTIFIER

In reply to saritr:
Download from the Resorces-tab. Scroll down there and you will see a link ‘zip-file’.
Click there and the download will start.

In reply to saritr:

You need to read the article that Dave pointed you to concerning packages.

You should not be compiling the individual class files.

Instead you should use a package file to encapsulate all of your agent’s class files:

File pakmx_pkg.sv:

package pakmx_pkg.sv
  import uvm_pkg::*;
  `include "uvm_macros.svh"
  `include "pakmx_config.sv"
  `include "pakmx_sequence.sv"
  `include "pakmx_agent.sv"
  `include "pakmx_env.sv"
  `include "pakmx_test.sv"
  `include "pakmx_driver.sv"
endpackage

Only compile the pakmx_pkg.sv file. DO NOT compile the individual files.

My guess is that you will still get errors because the include is order dependent.

In reply to cgales:
Can you explain me the adventage/motivation of using pkg instead of compile the indicidual class files?

In reply to saritr:

You really need to read the article that Dave points to in his above response. You should also read the Verification Horizons article that is also mentioned. They will explain all the reasons you should be using packages.

Hi,
i’am new in uvm
import uvm_pkg::*;
include "uvm_macros.svh" include “shift_register.sv”
include "shift_register_intf.sv" //include “shift_register_uvm_pkg.sv”

module shift_tb_top();
import shift_register_uvm_pkg::*;
shift_register_intf shift_intf();

bit clk;
bit[7:0] si;
bit rst;
bit so;
bit[7:0] temp1;
bit[7:0] temp2;

shift_register dut(.clk(shift_intf.clk),.si(shift_intf.si),.rst(shift_intf.rst),.temp1(shift_intf.temp1),.temp2(shift_intf.temp2),.so(shift_intf.so));
initial begin
uvm_config_db#(virtual shift_register_intf)::set(null,“*”,“shift_register_intf”,shift_intf);

run_test("shift_register_test");


  end

initial begin
$wlfdumpvars();
end
endmodule

but get the error.pls give ideaStart time: 11:50:59 on Aug 02,2017
vlog shift_tb_top.sv
** Note: (vlog-2286) Using implicit +incdir+/tools/mentor/Questa_10.3c_ultra/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
– Compiling interface shift_register_intf
** Error: shift_tb_top.sv(10): (vlog-13006) Could not find the package (shift_register_uvm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

In reply to baladevi:

You are doing strange things with your includes and imports. I see this quite often here and would be interested who is teaching this.
But the reason for your error is you have commented out the line with the include of “shift_register_uvm_pkg.sv”.
The simulator cannot find this package in work.