Hi,
i’am new in uvm
import uvm_pkg::*;
include "uvm_macros.svh" include “shift_register.sv”
include "shift_register_intf.sv" //include “shift_register_uvm_pkg.sv”
module shift_tb_top();
import shift_register_uvm_pkg::*;
shift_register_intf shift_intf();
bit clk;
bit[7:0] si;
bit rst;
bit so;
bit[7:0] temp1;
bit[7:0] temp2;
shift_register dut(.clk(shift_intf.clk),.si(shift_intf.si),.rst(shift_intf.rst),.temp1(shift_intf.temp1),.temp2(shift_intf.temp2),.so(shift_intf.so));
initial begin
uvm_config_db#(virtual shift_register_intf)::set(null,“*”,“shift_register_intf”,shift_intf);
run_test("shift_register_test");
end
initial begin
$wlfdumpvars();
end
endmodule
but get the error.pls give ideaStart time: 11:50:59 on Aug 02,2017
vlog shift_tb_top.sv
** Note: (vlog-2286) Using implicit +incdir+/tools/mentor/Questa_10.3c_ultra/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
– Compiling interface shift_register_intf
** Error: shift_tb_top.sv(10): (vlog-13006) Could not find the package (shift_register_uvm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.