I was reading LRM 1800-2012.pdf for timescale precedence and it seems following lines contradictory.
LRM Section - 3.14.2.3
b) Else, if a timescale directive has been previously specified (within the compilation unit), then the time unit shall be set to the units of the last timescale directive
The time unit of the compilation-unit scope can only be set by a timeunit declaration, not a `timescale
directive. If it is not specified, then the default time unit shall be used.
It is specified this way to be backward compatible with Verilog.
The `timescale compiler directive may only be specified outside a module, package, or interface (design units). But that directive only effects the design units that follow it; it has no effect on code that might exist in the compilation unit scope (outside a design unit). The compilation unit scope can only have a single time specification.
Thanks dave. To follow your answer.
In the following example i have define `timescale compiler directive in adice.v and compiled and elaborated both adice.v and file2.v together as single compilation unit.
The timescale of file2.v is 1ps/1ps?
file - adice.v
`timescale 1ps/1ps
module adice;
int i, j
file2 file2(.i(i), .j(j));
endmodule
file - file2.v
module file2(input i, output o);
initial $printtimescale
endmodule
Your files should have a *.sv file suffix to be recognized as SystemVerilog. Do not use a switch to make everything compile as SystemVerilog — you will run into trouble if you ever have to incorporate legacy Verilog code. All Verilog files are part of the same compilation unit, whereas your tools have a choice to make each SV file a separate compilation unit (like C/C++) or all the same unit.
The order that you compile each file matters when you use compiler directives like `timescale. Elaboration hierarchy does not matter. If you compile file2 last, it has the timescale 1ps/1ps.
I have changed the file extension to .sv and didn’t give switch(-sv) to make everything compile as system verilog.
I compile fil2.sv as the last file and it has timescale 1ps/1ps but as per my understanding from LRM, the class file2.sv should take the default timescale 1ns/1ns.
LRM - The time unit of the compilation-unit scope can only be set by a timeunit declaration, not a `timescale directive.
You have no code in the compilation unit scope, so that LRM rule does not apply here.
This forum is not for tool specific behavior, but the default timescale is tool dependant. Also, the default behavior for whether each file on the command line becomes a separate compilation unit is also tool dependent. To be sure, use separate command lines to compile each file.
Just to clarify, what is the persistence of timeunit/timeprecision - containing module? Until another `timescale/timeunit/etc is encountered? Finally, LRM indicates usage of timeunit is all or none, any other ussage is an error. That seems to be tool-dependent as I’m not seeing an error when only my top TB has it.
In reply to mchal9thou:
The
timeunit construct takes precedence over
`timescale compiler directives. When placed at the beginning of a module, it only applies to that module and has no effect on later modules, or nested module instances. If you put a
timeunit construct outside a module, it applies to all modules declared in that compilation unit. You can only have one ‘timeunit’ per compilation unit.
The intent was that `timescale is for legacy Verilog code. Once you start using timeunit, you should not mix the two.
In reply to SumitGoel:
It is specified this way to be backward compatible with Verilog.
The `timescale compiler directive may only be specified outside a module, package, or interface (design units). But that directive only effects the design units that follow it; it has no effect on code that might exist in the compilation unit scope (outside a design unit). The compilation unit scope can only have a single time specification.
Dear Dave,
If we have more than 1 `timescale declare on testbench (1 on top_tb, others are declared on other module files. THen which timescale should be used on this test bench? It will be the last one that declared before module or the 1st will be?
A module gets its time scale from the last timescale directive that precedes it. There is no global time scale for the testbench. The SystemVerilog timeunit construct takes precedence over timescale.