In reply to mchal9thou:
The
timeunit construct takes precedence over
`timescale compiler directives. When placed at the beginning of a module, it only applies to that module and has no effect on later modules, or nested module instances. If you put a
timeunit construct outside a module, it applies to all modules declared in that compilation unit. You can only have one ‘timeunit’ per compilation unit.
The intent was that `timescale is for legacy Verilog code. Once you start using timeunit, you should not mix the two.