In reply to dave_59:
In reply to SumitGoel:
It is specified this way to be backward compatible with Verilog.
The `timescale compiler directive may only be specified outside a module, package, or interface (design units). But that directive only effects the design units that follow it; it has no effect on code that might exist in the compilation unit scope (outside a design unit). The compilation unit scope can only have a single time specification.
Dear Dave,
If we have more than 1 `timescale declare on testbench (1 on top_tb, others are declared on other module files. THen which timescale should be used on this test bench? It will be the last one that declared before module or the 1st will be?