In reply to Tosado Kaiser:
A module gets its time scale from the last timescale directive that precedes it. There is no global time scale for the testbench. The SystemVerilog timeunit construct takes precedence over timescale.
In reply to Tosado Kaiser:
A module gets its time scale from the last timescale directive that precedes it. There is no global time scale for the testbench. The SystemVerilog timeunit construct takes precedence over timescale.