In reply to SumitGoel:
Your files should have a *.sv file suffix to be recognized as SystemVerilog. Do not use a switch to make everything compile as SystemVerilog — you will run into trouble if you ever have to incorporate legacy Verilog code. All Verilog files are part of the same compilation unit, whereas your tools have a choice to make each SV file a separate compilation unit (like C/C++) or all the same unit.
The order that you compile each file matters when you use compiler directives like `timescale. Elaboration hierarchy does not matter. If you compile file2 last, it has the timescale 1ps/1ps.