Can anyone give more clarity on BURST TRANSFER for AHB bus ?
I got to know the what is WRAP4, WRAP8, WRAP 16.
But don’t know, how to use it, or build logic for it.
For eg. If my address is 0x0E, and the transfer is WRAP4 and HALFWORD transfer size,
So the sequence can be 0x0E → 0x00 → 0x02 → 0x04.
Is this sequence correct ?
Similarly, for WRAP8, HALFWORD.
if sequence if 0x0E → 0x00 → 0x02 → 0x04 → 0x06 → 0x08 ->0x0A ->0x0C.
IS this sequence correct ?
What to do if it is WRAP8 and WORD transfer size ?
Similarly, can any one inform example for WRAP16 - HALFWORD or WORD transfer size.
I will give examples for your clarification:-
example1:- wrap4 halfword and starting address is 0x0E.
steps:
1> count the size of transfer 4 * 2 = 8 bytes.
2> assume that the memory is divided in the segments of 8 bytes.
so trnsfers can be stored from 0 to 7 or 8 to 15 or 16 to 23 etc. address locations (here address locations are in decimal).
3>address 0x0E
0x08
0x0A
0x0C
example2:- WRAP16 - HALFWORD (as you asked)
steps:
1> count the size of transfer 16 * 2 = 32 bytes.
2> assume that the memory is divided in the segments of 8 bytes.
so trnsfers can be stored from 0 to 31 or 32 to 63 or 64 to 95 etc. address locations (here address locations are in decimal).
3>address 0x0E (starting address)
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
Hello ANKIT PANDEY.
Thank you for giving me a genuine suggestion.
I was able to get the logic, for all possible logic, other than WORD WRAP8 , HALFWORD WRAP4 and WORD WRAP16 logic.
Can you please provide me how to build a logic for checking the 32 address boundary and 64 address boundary.
I am not taking the DOUBLEWORD,WORD4,WORD8,BIT_512,BIT_1024 in to consideration, as for AHB, it is mentioned that the transfer of size must be less than the DATA BUS Width.
Can you please provide me how to build a logic for checking the 32 address boundary and 64 address boundary.
can you explain this what you are asking.(if possible give me example)
I got the logic,
I was searching for a logic, which could detect the window range for input address.
for eg, if my address is 0x86, than it belongs to 80-BF address window.
So i was searching for this logic.
Anyways, i got the logic and implemented it and it works perfectly.
Thank you once again.
IN Burst type 001: INCR UNDEF length.
Who decides that how long the transfer should be performed ?
On what parameter the transfer continues ?
I mean, how long should it do the increment transfer ?
Master can continue as long as master wants but it should not cross 1024KB boundary(a/c to ahb spec) in one burst.
I did not work on design side so about parameters I don’t know much, but I feel master will have some registers from which maste knows how long it has to continue.
Suppose you want to transfer 2000KB with undefined INCR than in first burst you cover 1024 and next burst you can cover rest.(you can do two back to back INCR burst).