Master can continue as long as master wants but it should not cross 1024KB boundary(a/c to ahb spec) in one burst.
I did not work on design side so about parameters I don’t know much, but I feel master will have some registers from which maste knows how long it has to continue.
Suppose you want to transfer 2000KB with undefined INCR than in first burst you cover 1024 and next burst you can cover rest.(you can do two back to back INCR burst).