UVM Framework | Verification Academy

Sessions

UVMF - Series Introduction

In this session, you are introduced to the UVM Framework and the list of sessions that comprise this video course.

UVMF - Overview

In this session, you will learn what the UVM Framework is, the functionality it provides, its testbench architecture, and available documentation and support.

Code Generation Introduction

Code Generation Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn why code generation can be a powerful tool and how to take advantage of it for the purposes of quickly producing a UVMF-based testbench.

Agents: Architecture and Operation

In this session, you will learn about components within a protocol agent and its associated bus functional models and the roles and responsibilities of these components including the abstraction level they operate at.

Interface Code Generation

In this session, you will learn the steps needed to produce code for an UVMF Interface using the generator.

Environments: Architecture and Operation

In this session, you will learn the roles and responsibilities of an environment within a simulation.

Scoreboards and Predictors

In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.

Questa® VIP Integration

In this session, you will learn how to integrate Questa® Verification IP within your UVMF testbench.

Environment Code Generation

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment and what parts of the generated output that you'll need to modify afterwards.

Testbench: Architecture and Operation

The UVMF testbench contains top level modules, top level sequence, top level environment, and top level configuration. In this session, you will learn about the architecture of a UVMF testbench and directory structure.

Bench Code Generation

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Bench and what parts of the generated output that you’ll need to modify afterwards.

Instantiating the DUT

In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench.

Adding Tests and Sequences

In this session, you will learn how to add sequences and test cases to a UVMF testbench using the example derived test and extended top level virtual sequence.

Sequence Categories

In this session, you will learn the roles and responsibilities of the sequence categories and that sequences within UVMF are divided into three categories: interface, environment, and testbench.

UVMF & Emulation

UVMF and Emulation Session | Subject Matter Expert - Michael Horn | UVM Framework Course

The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.

Running Simulations

In this session, you will learn how to run individual UVMF simulations in both batch and debug mode as well as how to configure and run a regression test suite using the Questa® Verification Run Manager.

Code Generation Guidelines

In this session, you will be given an overview of the flow used to generate a working simulation using the UVMF code generator.

Stimulus and Analysis Data Flow

In this session, you will be given an overview of the stimulus and analysis flow within the UVM Framework.

Code Generation Merging

In this session you will learn about UVMF code generation capabilities that allow you to quickly produce new iterations of generated code that automatically transfer previous manual edits from earlier versions.