New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Mark Peryer

Mark Peryer is a Verification Methodologist within the Design Verification and Technology division at Siemens EDA and is responsible for developing and deploying verification methodologies and solutions. He developed his first verification environment for a graphics processor in the mid-eighties and although the languages and the techniques have changed, he has continued to work on hairy verification problems ever since. Mark is the author of many conference papers, articles and training classes and holds an honors degree in Electronic Engineering from Southampton University.

Content by Mark Peryer

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