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In preparing this issue of Verification Horizons, I was planning to write my Editor's Note, once again, about the Patriots winning the Super Bowl. I had it all worked out how I was going to write about the need for preparation, planning, and execution and how a long-established methodology can bring disparate pieces of a project together to meet requirements and achieve your team goals. It was going to be great.

And then the Patriots lost.

To be fair, as a former colleague of mine wrote to me after the game, it was the most impressive losing effort in Super Bowl history, but it was still a loss. With the Patriots driving for what would have been the winning touchdown in the closing minutes, the Eagles—for the first and only time in the game—got to Tom Brady and forced a fumble that effectively ended the game. From the perspective of a Patriots fan, it was the football equivalent of a bug escaping into production hardware: a disaster.

Of course, the difference between football and verification is that in verification there's not another team trying to beat you (with the possible exception of hackers trying to break your security and data encryption, but that's another story). In verification, preparation, planning, and execution together with the right methodology, will get you to tape-out with a functionally correct design that meets all your requirements.

But just like the Patriots will have to reexamine things a bit and improve for next season, this DVCon edition of Verification Horizons should give you some valuable insights into how you might improve your own verification efforts.

Just like a football team needs to make adjustments dynamically, our first article, from Portable Stimulus Guru Matthew Ballance, shows you how you can "Make your Constraints More Dynamic with Portable Stimulus." In Portable Stimulus, dynamic constraints give you another dimension of abstraction in describing the algebraic relationships between elements of your verification intent model. The article gives you a great introduction to this powerful part of the new Portable Stimulus Standard (PSS) from Accellera.

Our next two articles, from the technical experts on our QVIP team, discuss some of the many benefits of Questa® Verification IP (QVIP) components. First, "Configuring Memory Read Completions Sent by PCIe® QVIP" provides a nice overview of the PCIe read request protocol and shows how our PCIe QVIP component is flexible enough to handle all variations of the protocol to suit the needs of your particular environment. In "SATA Specification 3.3 Gaps Filled by SATA QVIP," we learn how a robustly-designed verification component can fill the gap when even the protocol spec itself has some issues. After an overview of the SATA protocol and an explanation of these gaps, you'll see how the SATA QVIP component addresses each of the gaps to allow you to design an efficient implementation of the protocol.

Our next article starts a multi-part series on Power-Aware Static Verification. In "Part 1: From Power Intent to Microarchitectural Checks of Low-Power Designs," we see how the Unified Power Format (UPF) defines the power intent for a design and how a power-aware static verification tool can analyze these structures to ensure that the intent is properly implemented. The article takes you through several of the checks that the tool performs and explains the value that each provides for you.

In our Partners' Corner, my old friend and assertions expert Ben Cohen shares his thoughts on an "SVA Alternative for Complex Assertions." In his vast experience, Ben has encountered some situations where pure SVA properties just weren't able to model the behaviors he needed to check, and this article explains how SystemVerilog tasks can be used to implement assertions when the need arises. I always enjoy Ben's unique perspective, and I'm sure you'll find this article interesting and informative.

Last but not least, we have "A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs" by our friend Mike Bartley of Test & Verification Solutions. Mike sets up his verification environment in unit- core- and SoC-level testbenches and walks you through the architecture and configuration of each level. I'm sure you'll find plenty of ideas that you'll be able to apply to your own environment, even if you're not verifying a RISC-V design. Just like pitchers and catchers reporting to baseball Spring Training, DVCon US is one of those annual events that hint that Spring is just around the corner.

As much as I was planning to wear my Patriots shirt to DVCon, I'll just have to break out the Red Sox shirt a bit earlier than usual. If you're at DVCon in San Jose February 26th – March 2nd, please stop by the Verification Academy booth or find me after one of the great technical sessions and say hi. If you're wearing an Eagles shirt, I may just walk away, though.

Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons