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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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July 2022 - Volume 18 Issue 2 (10)

June 2013 - Volume 9 Issue 2 (10)

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1800.2 (9)

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June 2012 - Volume 8 Issue 2 (9)

June 2014 - Volume 10 Issue 2 (9)

June 2018 - Volume 14 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

OSCI (8)

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UCIe 2.0 (8)

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XML (8)

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ADAS (7)

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Bind (7)

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Instance (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

Layering (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

Non-Determinism (7)

November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Order Property Pattern (7)

Parameterized Tests (7)

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Predictors (7)

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Supply Network (7)

Syntax (7)

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Testbench Customization in UVM (7)

Tool Qualification (7)

UVVM (7)

Unified Coverage Database (7)

VA Live 2023 - Huntsville (7)

Verbosity (7)

Verification Models (7)

Verification Quality (7)

X-Effects (7)

AEH (6)

Address Mapping (6)

Appendix (6)

Artificial Neural Network (6)

Behavioral Modeling (6)

Bugged Out Podcast (6)

Build Phase (6)

Clock Propagation (6)

Concurrent Processes (6)

Coverage Holes (6)

Coverage Intent (6)

Creating and Using a Test Plan (6)

DAC 2018 (6)

December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Defect Coverage (6)

Design Completion (6)

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Development Environment (6)

Distributed Resource Management (6)

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Dynamic Power (6)

Electronic Hardware (6)

Flip-Flop (6)

Front and Back Door (6)

HDM (6)

HVL (6)

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Implicit/Explicit (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

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Pre-Silicon (6)

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Random Faults (6)

Respins (6)

Semiconductor (6)

Sequence Library (6)

Split Transactor (6)

Static Analyses (6)

Static RDC (6)

Stimulus Free Verification (6)

Tessent Test Solutions (6)

UCIe 3.0 (6)

UVM Forum (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VA Live 2026 - Hudson (6)

VHDL Testbench (6)

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YAML (6)

osmosis 2024 A&D (6)

Advance Your Verification Methodology (5)

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Debug Challenges (5)

December 2019 - Volume 15 Issue 3 (5)

Design Cycle (5)

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Error (5)

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FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Methods (5)

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Function (5)

HBM (5)

HBM4 (5)

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High-Speed (5)

IDE (5)

IP Blocks (5)

In-Circuit Emulation (5)

Integration Level (5)

JEDEC (5)

LRM (5)

Low Latency (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

Memory-Mapped Registers (5)

Metastability Injection (5)

Model Context Protocol (5)

NVM Express (5)

Namespaces (5)

Non-Pipelined (5)

Non-Reset (5)

Partitioning (5)

Processor Core Verification (5)

Quirky (5)

Repository (5)

Reset Signal (5)

SFV (5)

SSD (5)

SVTB (5)

SVUnit (5)

Simulink (5)

State-Based Model (5)

Stimulus Pattern (5)

Test Coverage (5)

Transaction-Based Acceleration (5)

UART (5)

UVC (5)

Unreachability (5)

Use Models (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

Verification Case Document (5)

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5G (4)

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Boolean (4)

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DVFS (4)

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Deprecated (4)

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Digital Domain (4)

DisplayPort (4)

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ECO (4)

ED-80 (4)

ENV Package (4)

Enumeration (4)

Equivalent RTL (4)

Fault Coverage (4)

Fault Detection (4)

Fault List (4)

Fibre Channel (4)

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GPU (4)

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IC Design (4)

ICE Mode (4)

IEEE (4)

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In-Circuit Simulation (4)

In-System Test (4)

Initial States (4)

Instantiate (4)

LFM (4)

Language Constructs (4)

Large Language Models (4)

Mathworks (4)

Mitigation Architecture (4)

Monitor (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

PHY (4)

Phase Objections (4)

Plusargs (4)

Power Constraints (4)

Protocol Checkers (4)

Proxy Class (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

Race Conditions (4)

Reconfiguration (4)

Reset Handling (4)

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Risk Mitigation (4)

Semantics (4)

Sequential Logic (4)

Specification Pattern (4)

Static Timing (4)

Stream (4)

Structural Checks (4)

Subscriber (4)

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Synergistic Verification (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Toolkit (4)

Top Down (4)

Transactors (4)

Trust Verification (4)

UCIS (4)

UEC (4)

UPF 3.0 (4)

UPF 4.0 (4)

USB (4)

UVM 1.1d (4)

UVM 1.2 (4)

UVM Monitor (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

VPM (4)

Vectors (4)

Verification Blueprint (4)

Verification Maturity (4)

Virtual Sequencers (4)

$display (3)

1.2 (3)

AMS Verification (3)

APB3 (3)

Abstract Class (3)

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Airborne Electronic Hardware (3)

Analysis Components (3)

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Autonomous Systems (3)

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Base Test (3)

BiQuad (3)

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Block Diagram (3)

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CDC Signals (3)

CSI-2 (3)

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Certification (3)

Clock Definitions (3)

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Clocking (3)

Code Quality (3)

Command Line Processor (3)

Connect Phase (3)

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Coroutines (3)

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Critical Storage (3)

Cross-Domain (3)

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Cutpoint (3)

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ESL (3)

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FWHW (3)

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Horizontal Reuse (3)

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Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

Lane Margining (3)

Level-shifter (3)

Load Balancing (3)

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MC2 (3)

MUX (3)

Mailboxes (3)

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Memory Debug (3)

Method (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observer (3)

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PCI-SIG (3)

PCIe Gen 8 (3)

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QFL (3)

Qrun (3)

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RISC-V Verification Interface (3)

RTL Emulation (3)

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Routines (3)

SDC (3)

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Security Coverage (3)

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Semaphores (3)

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Serial Interface (3)

Shift Left (3)

Sign-Off Methodology (3)

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Single Step Debug (3)

Singleton (3)

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Static Lists (3)

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Subsystem (3)

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TBX (3)

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Timing Analysis (3)

Timing Integrity (3)

Tool Optimization (3)

Transaction Layer (3)

Transfer Protocols (3)

Transitive (3)

Type Casting (3)

Typedef (3)

UEFI (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unidirectional (3)

Unreachable Code (3)

VHDL-2019 (3)

VIP - 3.1 (3)

Values (3)

VbyOne (3)

Verification Bottleneck (3)

Verification Framework (3)

Verification Integrity (3)

View Modes (3)

Wave Window (3)

Wrapper (3)

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February 2013

OVM to UVM Migration, or There and Back Again: A Consultant’s Tale
UVM - Universal Verification Methodology Feb 25, 2013 Mark Litterick - Verilab Gmbh Article
Verification Horizons - Volume 9, Issue 1
Standards Feb 01, 2013 Tom Fitzpatrick pdf

January 2013

VHDL-2008 Overview
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Testbench Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
RTL Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Operator Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Package Type Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Fixed Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Floating Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
VHDL 2008: Why It Matters
VHDL 2008 Jan 17, 2013 Jim Lewis Track

December 2012

Improve AMS Verification Quality
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Track
Overview to Improve AMS Quality
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Session
Analog Aspects in AMS
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Session
Extend Power Aware Verification to AMS
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Session
Extend Structured Formal Verification to AMS
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Session
Questa ADMS: AMS Quality
Analog Mixed-Signal Verification Dec 01, 2012 Ahmed Eisawy Session