Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks
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July 2021
March 2021
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Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
High-Level Synthesis Mar 31, 2021 pdf -
Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
High-Level Synthesis Mar 31, 2021 Seminar -
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Practical Flows for Continuous Integration: Making the Most of Your EDA Tools
Questa Design Solutions Mar 16, 2021 Webinar -
The Six Steps Of RISC-V Processor Verification Including Vector Extensions
Verification IP Mar 03, 2021 Article
February 2021
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I'm Excited About Formal...My Journey From Skeptic to Believer
Formal Verification Feb 26, 2021 Webinar
October 2020
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Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
Debug Oct 27, 2020 Webinar
September 2019
June 2019
February 2019
June 2018
September 2017
June 2017
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RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success
Clock-Domain Crossing Jun 28, 2017 Article -
June 2016
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Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
Functional Safety Jun 01, 2016 Article
March 2016
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An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
UVM - Universal Verification Methodology Mar 02, 2016 Article -
