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March 2024 - Volume 20 Issue 1 (1)

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Show Less

March 2019

Formal Apps Take the Bias Out of Functional Verification
Formal Verification Mar 13, 2019 Bill Au pdf
Technical Paper: UVM and C Tests - Perfect Together
Standards Mar 03, 2019 pdf
Effective Elements List and Transitive Natures of UPF Commands
Low Power Feb 28, 2019 pdf

February 2019

The Big Brain Theory: Visualizing SoC Design and Verification Data
Verification Management Feb 28, 2019 pdf
Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Rohit Jain pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich pdf
Boosting Regression Throughput by Reusing Setup Phase Simulation
FPGA Verification Feb 28, 2019 Rohit Jain pdf
Clock-Domain Crossing Challenges in Latch Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara pdf
Low Power Apps: Shaping the Future of Low Power Verification
Low Power Feb 28, 2019 pdf
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung pdf
Formal Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2019 Doug Smith pdf
Technical Paper: Are You Smarter Than Your Testbench? With a Little Work You Can Be
Standards Feb 28, 2019 pdf
Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich pdf
Technical Paper: UVM Sans UVM: An Approach to Automating UVM Testbench Writing
Standards Feb 28, 2019 pdf
Choosing a Format for the Portable Stimulus Specification
Portable Stimulus Feb 22, 2019 Matthew Ballance pdf

January 2019

Accelerating Verification through Verification IP, Configurator and UVM Framework
Verification IP Jan 24, 2019 Sharath Kannareddy pdf
Making Verification Fun Again
UVM Framework Jan 24, 2019 Jonathan Craft pdf
Verification Acceleration for FPGA Designs with Matlab
Acceleration Jan 24, 2019 Jerry Grula - Siemens Eda pdf
Welcome & Overview
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf
ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

December 2018

C Stimulus Package (.tgz)
UVM - Universal Verification Methodology Dec 04, 2018 Verification Methodology Team tar

October 2018

Planning for DO-254
Functional Safety Oct 10, 2018 Byron Brinson pdf
DO-254 in Simple Terms
Functional Safety Oct 04, 2018 Byron Brinson pdf

September 2018

UVM 1800.2 and the New & Improved Cookbook
UVM - Universal Verification Methodology Sep 27, 2018 pdf
A Fresh Look at Creating a UVM Environment - UVM Framework
UVM Framework Sep 27, 2018 pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

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AI is Changing Verification | Interview with Abhi Kolpekwar

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