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September 2021 - Volume 17 Issue 2 (7)

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Show Less

September 2021

Python and the UVM
Python Sep 09, 2021 Ray Salemi link
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

August 2021

UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
UVM Framework Aug 05, 2021 Pedram Riahi - Raytheon Webinar

July 2021

Managing Requirements in a Functional Safety Environment
Functional Safety Jul 29, 2021 Thorsten Stahlberg - Siemens Eda Webinar
Digital Functional Verification for Safety-Critical Automotive Applications
Functional Safety Jul 29, 2021 Michael Bierl - Siemens Eda Webinar
CDC Verification: Beyond Structural Analysis
Clock-Domain Crossing Jul 29, 2021 Mark Handover Webinar
Creating a Fast and Productive USB4 Verification Environment
Verification IP Jul 29, 2021 Didan Francis pdf
Creating a Fast and Productive USB4 Verification Environment
Verification IP Jul 29, 2021 Didan Francis Webinar
UVM Framework Release 2021.3
UVM Framework Jul 13, 2021 Bob Oden tar

May 2021

Introducing Transactions | Japanese
UVM - Universal Verification Methodology May 28, 2021 Tom Fitzpatrick pdf
How TLM Works
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
The Proper Care and Feeding of Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
The Three Witches Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing May 18, 2021 Ping Yeung pdf
Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 pdf

April 2021

A Guide to QVIP Workflow and Debug for PCIe®
Verification IP Apr 08, 2021 Akshay Sarup Webinar
Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 link
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 pdf
Making Your DPI-C Interface a Fast River of Data
SystemVerilog Mar 31, 2021 Rich Edelman Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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